5 config CREATE_ARCH_SYMLINK
8 config HAVE_ARCH_IOREMAP
11 config SYS_CACHE_SHIFT_4
14 config SYS_CACHE_SHIFT_5
17 config SYS_CACHE_SHIFT_6
20 config SYS_CACHE_SHIFT_7
23 config SYS_CACHELINE_SIZE
25 default 128 if SYS_CACHE_SHIFT_7
26 default 64 if SYS_CACHE_SHIFT_6
27 default 32 if SYS_CACHE_SHIFT_5
28 default 16 if SYS_CACHE_SHIFT_4
32 config LINKER_LIST_ALIGN
35 default 8 if ARM64 || X86
38 Force the each linker list to be aligned to this boundary. This
39 is required if ll_entry_get() is used, since otherwise the linker
40 may add padding into the table, thus breaking it.
41 See linker_lists.rst for full details.
44 prompt "Architecture select"
48 bool "ARC architecture"
52 select HAVE_PRIVATE_LIBGCC
53 select SUPPORT_OF_CONTROL
54 select SYS_CACHE_SHIFT_7
56 select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
57 select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
60 bool "ARM architecture"
61 select ARCH_SUPPORTS_LTO
62 select CREATE_ARCH_SYMLINK
63 select HAVE_PRIVATE_LIBGCC if !ARM64
65 select SUPPORT_OF_CONTROL
68 bool "M68000 architecture"
69 select HAVE_PRIVATE_LIBGCC
70 select NEEDS_MANUAL_RELOC
71 select SYS_BOOT_GET_CMDLINE
72 select SYS_BOOT_GET_KBD
73 select SYS_CACHE_SHIFT_4
74 select SUPPORT_OF_CONTROL
77 bool "MicroBlaze architecture"
78 select SUPPORT_OF_CONTROL
80 imply SPL_REGMAP if SPL
81 imply SPL_TIMER if SPL
86 bool "MIPS architecture"
87 select HAVE_ARCH_IOREMAP
88 select HAVE_PRIVATE_LIBGCC
89 select SUPPORT_OF_CONTROL
90 select SPL_SEPARATE_BSS if SPL
93 bool "Nios II architecture"
98 select SUPPORT_OF_CONTROL
102 bool "PowerPC architecture"
103 select HAVE_PRIVATE_LIBGCC
104 select SUPPORT_OF_CONTROL
105 select SYS_BOOT_GET_CMDLINE
106 select SYS_BOOT_GET_KBD
109 bool "RISC-V architecture"
110 select CREATE_ARCH_SYMLINK
111 select SUPPORT_OF_CONTROL
115 imply SPL_SEPARATE_BSS if SPL
127 imply SPL_LIBCOMMON_SUPPORT
128 imply SPL_LIBGENERIC_SUPPORT
134 select ARCH_SUPPORTS_LTO
135 select BOARD_LATE_INIT
140 select DM_FUZZING_ENGINE
148 select GZIP_COMPRESSED
151 select OF_BOARD_SETUP
154 select SUPPORT_OF_CONTROL
155 select SYSRESET_CMD_POWEROFF
156 select SYS_CACHE_SHIFT_4
158 select SUPPORT_EXTENSION_SCAN
175 imply FUZZING_ENGINE_SANDBOX
182 imply PARTITION_TYPE_GUID
185 imply UDP_FUNCTION_FASTBOOT
198 imply ACPI_PMC_SANDBOX
208 imply GENERATE_ACPI_TABLE
212 bool "SuperH architecture"
213 select HAVE_PRIVATE_LIBGCC
214 select SUPPORT_OF_CONTROL
217 bool "x86 architecture"
220 select CREATE_ARCH_SYMLINK
222 select HAVE_ARCH_IOMAP
223 select HAVE_PRIVATE_LIBGCC
227 select SUPPORT_OF_CONTROL
228 select SYS_CACHE_SHIFT_6
230 select USE_PRIVATE_LIBGCC
233 imply HAS_ROM if X86_RESET_VECTOR
236 imply CMD_FPGA_LOADMK
258 imply USB_ETHER_SMSC95XX
263 imply ACPIGEN if !QEMU && !EFI_APP
264 imply SYSINFO if GENERATE_SMBIOS_TABLE
265 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
268 # Thing to enable for when SPL/TPL are enabled: SPL
271 imply SPL_DRIVERS_MISC
274 imply SPL_LIBCOMMON_SUPPORT
275 imply SPL_LIBGENERIC_SUPPORT
277 imply SPL_SPI_FLASH_SUPPORT
285 imply TPL_DRIVERS_MISC
288 imply TPL_LIBCOMMON_SUPPORT
289 imply TPL_LIBGENERIC_SUPPORT
297 bool "Xtensa architecture"
298 select CREATE_ARCH_SYMLINK
299 select SUPPORT_OF_CONTROL
306 This option should contain the architecture name to build the
307 appropriate arch/<CONFIG_SYS_ARCH> directory.
308 All the architectures should specify this option correctly.
313 This option should contain the CPU name to build the correct
314 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
316 This is optional. For those targets without the CPU directory,
317 leave this option empty.
322 This option should contain the SoC name to build the directory
323 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
325 This is optional. For those targets without the SoC directory,
326 leave this option empty.
331 This option should contain the vendor name of the target board.
333 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
334 directory is compiled.
335 If CONFIG_SYS_BOARD is also set, the sources under
336 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
338 This is optional. For those targets without the vendor directory,
339 leave this option empty.
344 This option should contain the name of the target board.
345 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
346 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
347 whether CONFIG_SYS_VENDOR is set or not.
349 This is optional. For those targets without the board directory,
350 leave this option empty.
352 config SYS_CONFIG_NAME
355 This option should contain the base name of board header file.
356 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
357 should be included from include/config.h.
359 config SYS_DISABLE_DCACHE_OPS
362 This option disables dcache flush and dcache invalidation
363 operations. For example, on coherent systems where cache
364 operatios are not required, enable this option to avoid them.
365 Note that, its up to the individual architectures to implement
369 hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
370 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
371 default 0xFF000000 if MPC8xx
372 default 0xF0000000 if ARCH_MPC8313
373 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
374 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
375 default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
376 ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
378 default SYS_CCSRBAR_DEFAULT
380 Address for the Internal Memory-Mapped Registers (IMMR) window used
381 to configure the features of many Freescale / NXP SoCs.
383 config MONITOR_IS_IN_RAM
384 bool "U-Boot is loaded in to RAM by a pre-loader"
385 depends on M68K || NIOS2
387 menu "Skipping low level initialization functions"
388 depends on ARM || MIPS || RISCV
390 config SKIP_LOWLEVEL_INIT
391 bool "Skip calls to certain low level initialization functions"
393 If enabled, then certain low level initializations (like setting up
394 the memory controller) are omitted and/or U-Boot does not relocate
396 Normally this variable MUST NOT be defined. The only exception is
397 when U-Boot is loaded (to RAM) by some other boot loader or by a
398 debugger which performs these initializations itself.
400 config SPL_SKIP_LOWLEVEL_INIT
401 bool "Skip calls to certain low level initialization functions in SPL"
404 If enabled, then certain low level initializations (like setting up
405 the memory controller) are omitted and/or U-Boot does not relocate
407 Normally this variable MUST NOT be defined. The only exception is
408 when U-Boot is loaded (to RAM) by some other boot loader or by a
409 debugger which performs these initializations itself.
411 config TPL_SKIP_LOWLEVEL_INIT
412 bool "Skip calls to certain low level initialization functions in TPL"
413 depends on SPL && ARM
415 If enabled, then certain low level initializations (like setting up
416 the memory controller) are omitted and/or U-Boot does not relocate
418 Normally this variable MUST NOT be defined. The only exception is
419 when U-Boot is loaded (to RAM) by some other boot loader or by a
420 debugger which performs these initializations itself.
422 config SKIP_LOWLEVEL_INIT_ONLY
423 bool "Skip call to lowlevel_init during early boot ONLY"
426 This allows just the call to lowlevel_init() to be skipped. The
427 normal CP15 init (such as enabling the instruction cache) is still
430 config SPL_SKIP_LOWLEVEL_INIT_ONLY
431 bool "Skip call to lowlevel_init during early SPL boot ONLY"
432 depends on SPL && ARM
434 This allows just the call to lowlevel_init() to be skipped. The
435 normal CP15 init (such as enabling the instruction cache) is still
438 config TPL_SKIP_LOWLEVEL_INIT_ONLY
439 bool "Skip call to lowlevel_init during early TPL boot ONLY"
440 depends on TPL && ARM
442 This allows just the call to lowlevel_init() to be skipped. The
443 normal CP15 init (such as enabling the instruction cache) is still
448 config SYS_HAS_NONCACHED_MEMORY
449 bool "Enable reserving a non-cached memory area for drivers"
450 depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
452 This is useful for drivers that would otherwise require a lot of
453 explicit cache maintenance. For some drivers it's also impossible to
454 properly maintain the cache. For example if the regions that need to
455 be flushed are not a multiple of the cache-line size, *and* padding
456 cannot be allocated between the regions to align them (i.e. if the
457 HW requires a contiguous array of regions, and the size of each
458 region is not cache-aligned), then a flush of one region may result
459 in overwriting data that hardware has written to another region in
460 the same cache-line. This can happen for example in network drivers
461 where descriptors for buffers are typically smaller than the CPU
462 cache-line (e.g. 16 bytes vs. 32 or 64 bytes).
464 config SYS_NONCACHED_MEMORY
465 hex "Size in bytes of the non-cached memory area"
466 depends on SYS_HAS_NONCACHED_MEMORY
469 Size of non-cached memory area. This area of memory will be typically
470 located right below the malloc() area and mapped uncached in the MMU.
472 source "arch/arc/Kconfig"
473 source "arch/arm/Kconfig"
474 source "arch/m68k/Kconfig"
475 source "arch/microblaze/Kconfig"
476 source "arch/mips/Kconfig"
477 source "arch/nios2/Kconfig"
478 source "arch/powerpc/Kconfig"
479 source "arch/sandbox/Kconfig"
480 source "arch/sh/Kconfig"
481 source "arch/x86/Kconfig"
482 source "arch/xtensa/Kconfig"
483 source "arch/riscv/Kconfig"
485 if ARM || M68K || PPC
487 source "arch/Kconfig.nxp"
491 source "board/keymile/Kconfig"
493 if MIPS || MICROBLAZE
496 prompt "Endianness selection"
498 Some MIPS boards can be configured for either little or big endian
499 byte order. These modes require different U-Boot images. In general there
500 is one preferred byteorder for a particular system but some systems are
501 just as commonly used in the one or the other endianness.
503 config SYS_BIG_ENDIAN
505 depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
507 config SYS_LITTLE_ENDIAN
509 depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE