5 config CREATE_ARCH_SYMLINK
8 config HAVE_ARCH_IOREMAP
11 config SYS_CACHE_SHIFT_4
14 config SYS_CACHE_SHIFT_5
17 config SYS_CACHE_SHIFT_6
20 config SYS_CACHE_SHIFT_7
23 config SYS_CACHELINE_SIZE
25 default 128 if SYS_CACHE_SHIFT_7
26 default 64 if SYS_CACHE_SHIFT_6
27 default 32 if SYS_CACHE_SHIFT_5
28 default 16 if SYS_CACHE_SHIFT_4
32 config LINKER_LIST_ALIGN
35 default 8 if ARM64 || X86
38 Force the each linker list to be aligned to this boundary. This
39 is required if ll_entry_get() is used, since otherwise the linker
40 may add padding into the table, thus breaking it.
41 See linker_lists.rst for full details.
44 prompt "Architecture select"
48 bool "ARC architecture"
52 select HAVE_PRIVATE_LIBGCC
53 select SUPPORT_OF_CONTROL
54 select SYS_CACHE_SHIFT_7
56 select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
57 select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
60 bool "ARM architecture"
61 select ARCH_SUPPORTS_LTO
62 select CREATE_ARCH_SYMLINK
63 select HAVE_PRIVATE_LIBGCC if !ARM64
65 select SUPPORT_OF_CONTROL
68 bool "M68000 architecture"
69 select HAVE_PRIVATE_LIBGCC
70 select USE_PRIVATE_LIBGCC
71 select NEEDS_MANUAL_RELOC
72 select SYS_BOOT_GET_CMDLINE
73 select SYS_BOOT_GET_KBD
74 select SYS_CACHE_SHIFT_4
75 select SUPPORT_OF_CONTROL
78 bool "MicroBlaze architecture"
79 select SUPPORT_OF_CONTROL
81 imply SPL_REGMAP if SPL
82 imply SPL_TIMER if SPL
87 bool "MIPS architecture"
88 select HAVE_ARCH_IOREMAP
89 select HAVE_PRIVATE_LIBGCC
90 select SUPPORT_OF_CONTROL
91 select SPL_SEPARATE_BSS if SPL
94 bool "Nios II architecture"
99 select SUPPORT_OF_CONTROL
103 bool "PowerPC architecture"
104 select HAVE_PRIVATE_LIBGCC
105 select SUPPORT_OF_CONTROL
106 select SYS_BOOT_GET_CMDLINE
107 select SYS_BOOT_GET_KBD
110 bool "RISC-V architecture"
111 select CREATE_ARCH_SYMLINK
112 select SUPPORT_OF_CONTROL
116 imply SPL_SEPARATE_BSS if SPL
128 imply SPL_LIBCOMMON_SUPPORT
129 imply SPL_LIBGENERIC_SUPPORT
135 select ARCH_SUPPORTS_LTO
136 select BOARD_LATE_INIT
141 select DM_FUZZING_ENGINE
149 select GZIP_COMPRESSED
152 select OF_BOARD_SETUP
155 select SUPPORT_OF_CONTROL
156 select SYSRESET_CMD_POWEROFF
157 select SYS_CACHE_SHIFT_4
159 select SUPPORT_EXTENSION_SCAN
176 imply FUZZING_ENGINE_SANDBOX
183 imply PARTITION_TYPE_GUID
186 imply UDP_FUNCTION_FASTBOOT
200 imply ACPI_PMC_SANDBOX
210 imply GENERATE_ACPI_TABLE
214 bool "SuperH architecture"
215 select HAVE_PRIVATE_LIBGCC
216 select SUPPORT_OF_CONTROL
219 bool "x86 architecture"
222 select CREATE_ARCH_SYMLINK
224 select HAVE_ARCH_IOMAP
225 select HAVE_PRIVATE_LIBGCC
229 select SUPPORT_OF_CONTROL
230 select SYS_CACHE_SHIFT_6
232 select USE_PRIVATE_LIBGCC
235 imply HAS_ROM if X86_RESET_VECTOR
238 imply CMD_FPGA_LOADMK
260 imply USB_ETHER_SMSC95XX
266 imply ACPIGEN if !QEMU && !EFI_APP
267 imply SYSINFO if GENERATE_SMBIOS_TABLE
268 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
271 # Thing to enable for when SPL/TPL are enabled: SPL
274 imply SPL_DRIVERS_MISC
277 imply SPL_LIBCOMMON_SUPPORT
278 imply SPL_LIBGENERIC_SUPPORT
280 imply SPL_SPI_FLASH_SUPPORT
288 imply TPL_DRIVERS_MISC
291 imply TPL_LIBCOMMON_SUPPORT
292 imply TPL_LIBGENERIC_SUPPORT
300 bool "Xtensa architecture"
301 select CREATE_ARCH_SYMLINK
302 select SUPPORT_OF_CONTROL
309 This option should contain the architecture name to build the
310 appropriate arch/<CONFIG_SYS_ARCH> directory.
311 All the architectures should specify this option correctly.
316 This option should contain the CPU name to build the correct
317 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
319 This is optional. For those targets without the CPU directory,
320 leave this option empty.
325 This option should contain the SoC name to build the directory
326 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
328 This is optional. For those targets without the SoC directory,
329 leave this option empty.
334 This option should contain the vendor name of the target board.
336 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
337 directory is compiled.
338 If CONFIG_SYS_BOARD is also set, the sources under
339 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
341 This is optional. For those targets without the vendor directory,
342 leave this option empty.
347 This option should contain the name of the target board.
348 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
349 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
350 whether CONFIG_SYS_VENDOR is set or not.
352 This is optional. For those targets without the board directory,
353 leave this option empty.
355 config SYS_CONFIG_NAME
358 This option should contain the base name of board header file.
359 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
360 should be included from include/config.h.
362 config SYS_DISABLE_DCACHE_OPS
365 This option disables dcache flush and dcache invalidation
366 operations. For example, on coherent systems where cache
367 operatios are not required, enable this option to avoid them.
368 Note that, its up to the individual architectures to implement
372 hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
373 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
374 default 0xFF000000 if MPC8xx
375 default 0xF0000000 if ARCH_MPC8313
376 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
377 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
378 default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
379 ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
381 default SYS_CCSRBAR_DEFAULT
383 Address for the Internal Memory-Mapped Registers (IMMR) window used
384 to configure the features of many Freescale / NXP SoCs.
386 config MONITOR_IS_IN_RAM
387 bool "U-Boot is loaded in to RAM by a pre-loader"
388 depends on M68K || NIOS2
390 menu "Skipping low level initialization functions"
391 depends on ARM || MIPS || RISCV
393 config SKIP_LOWLEVEL_INIT
394 bool "Skip calls to certain low level initialization functions"
396 If enabled, then certain low level initializations (like setting up
397 the memory controller) are omitted and/or U-Boot does not relocate
399 Normally this variable MUST NOT be defined. The only exception is
400 when U-Boot is loaded (to RAM) by some other boot loader or by a
401 debugger which performs these initializations itself.
403 config SPL_SKIP_LOWLEVEL_INIT
404 bool "Skip calls to certain low level initialization functions in SPL"
407 If enabled, then certain low level initializations (like setting up
408 the memory controller) are omitted and/or U-Boot does not relocate
410 Normally this variable MUST NOT be defined. The only exception is
411 when U-Boot is loaded (to RAM) by some other boot loader or by a
412 debugger which performs these initializations itself.
414 config TPL_SKIP_LOWLEVEL_INIT
415 bool "Skip calls to certain low level initialization functions in TPL"
416 depends on SPL && ARM
418 If enabled, then certain low level initializations (like setting up
419 the memory controller) are omitted and/or U-Boot does not relocate
421 Normally this variable MUST NOT be defined. The only exception is
422 when U-Boot is loaded (to RAM) by some other boot loader or by a
423 debugger which performs these initializations itself.
425 config SKIP_LOWLEVEL_INIT_ONLY
426 bool "Skip call to lowlevel_init during early boot ONLY"
429 This allows just the call to lowlevel_init() to be skipped. The
430 normal CP15 init (such as enabling the instruction cache) is still
433 config SPL_SKIP_LOWLEVEL_INIT_ONLY
434 bool "Skip call to lowlevel_init during early SPL boot ONLY"
435 depends on SPL && ARM
437 This allows just the call to lowlevel_init() to be skipped. The
438 normal CP15 init (such as enabling the instruction cache) is still
441 config TPL_SKIP_LOWLEVEL_INIT_ONLY
442 bool "Skip call to lowlevel_init during early TPL boot ONLY"
443 depends on TPL && ARM
445 This allows just the call to lowlevel_init() to be skipped. The
446 normal CP15 init (such as enabling the instruction cache) is still
451 config SYS_HAS_NONCACHED_MEMORY
452 bool "Enable reserving a non-cached memory area for drivers"
453 depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
455 This is useful for drivers that would otherwise require a lot of
456 explicit cache maintenance. For some drivers it's also impossible to
457 properly maintain the cache. For example if the regions that need to
458 be flushed are not a multiple of the cache-line size, *and* padding
459 cannot be allocated between the regions to align them (i.e. if the
460 HW requires a contiguous array of regions, and the size of each
461 region is not cache-aligned), then a flush of one region may result
462 in overwriting data that hardware has written to another region in
463 the same cache-line. This can happen for example in network drivers
464 where descriptors for buffers are typically smaller than the CPU
465 cache-line (e.g. 16 bytes vs. 32 or 64 bytes).
467 config SYS_NONCACHED_MEMORY
468 hex "Size in bytes of the non-cached memory area"
469 depends on SYS_HAS_NONCACHED_MEMORY
472 Size of non-cached memory area. This area of memory will be typically
473 located right below the malloc() area and mapped uncached in the MMU.
475 source "arch/arc/Kconfig"
476 source "arch/arm/Kconfig"
477 source "arch/m68k/Kconfig"
478 source "arch/microblaze/Kconfig"
479 source "arch/mips/Kconfig"
480 source "arch/nios2/Kconfig"
481 source "arch/powerpc/Kconfig"
482 source "arch/sandbox/Kconfig"
483 source "arch/sh/Kconfig"
484 source "arch/x86/Kconfig"
485 source "arch/xtensa/Kconfig"
486 source "arch/riscv/Kconfig"
488 if ARM || M68K || PPC
490 source "arch/Kconfig.nxp"
494 source "board/keymile/Kconfig"
496 if MIPS || MICROBLAZE
499 prompt "Endianness selection"
501 Some MIPS boards can be configured for either little or big endian
502 byte order. These modes require different U-Boot images. In general there
503 is one preferred byteorder for a particular system but some systems are
504 just as commonly used in the one or the other endianness.
506 config SYS_BIG_ENDIAN
508 depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
510 config SYS_LITTLE_ENDIAN
512 depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE