5 config CREATE_ARCH_SYMLINK
8 config HAVE_ARCH_IOREMAP
11 config SYS_CACHE_SHIFT_4
14 config SYS_CACHE_SHIFT_5
17 config SYS_CACHE_SHIFT_6
20 config SYS_CACHE_SHIFT_7
23 config SYS_CACHELINE_SIZE
25 default 128 if SYS_CACHE_SHIFT_7
26 default 64 if SYS_CACHE_SHIFT_6
27 default 32 if SYS_CACHE_SHIFT_5
28 default 16 if SYS_CACHE_SHIFT_4
32 config LINKER_LIST_ALIGN
35 default 8 if ARM64 || X86
38 Force the each linker list to be aligned to this boundary. This
39 is required if ll_entry_get() is used, since otherwise the linker
40 may add padding into the table, thus breaking it.
41 See linker_lists.rst for full details.
44 prompt "Architecture select"
48 bool "ARC architecture"
52 select HAVE_PRIVATE_LIBGCC
53 select SUPPORT_OF_CONTROL
54 select SYS_CACHE_SHIFT_7
58 bool "ARM architecture"
59 select ARCH_SUPPORTS_LTO
60 select CREATE_ARCH_SYMLINK
61 select HAVE_PRIVATE_LIBGCC if !ARM64
63 select SUPPORT_OF_CONTROL
66 bool "M68000 architecture"
67 select HAVE_PRIVATE_LIBGCC
68 select NEEDS_MANUAL_RELOC
69 select SYS_BOOT_GET_CMDLINE
70 select SYS_BOOT_GET_KBD
71 select SYS_CACHE_SHIFT_4
72 select SUPPORT_OF_CONTROL
75 bool "MicroBlaze architecture"
76 select SUPPORT_OF_CONTROL
78 imply SPL_REGMAP if SPL
79 imply SPL_TIMER if SPL
84 bool "MIPS architecture"
85 select HAVE_ARCH_IOREMAP
86 select HAVE_PRIVATE_LIBGCC
87 select SUPPORT_OF_CONTROL
88 select SPL_SEPARATE_BSS if SPL
91 bool "Nios II architecture"
96 select SUPPORT_OF_CONTROL
100 bool "PowerPC architecture"
101 select HAVE_PRIVATE_LIBGCC
102 select SUPPORT_OF_CONTROL
103 select SYS_BOOT_GET_CMDLINE
104 select SYS_BOOT_GET_KBD
107 bool "RISC-V architecture"
108 select CREATE_ARCH_SYMLINK
109 select SUPPORT_OF_CONTROL
112 select SPL_SEPARATE_BSS if SPL
126 imply SPL_LIBCOMMON_SUPPORT
127 imply SPL_LIBGENERIC_SUPPORT
133 select ARCH_SUPPORTS_LTO
134 select BOARD_LATE_INIT
138 select DM_FUZZING_ENGINE
146 select GZIP_COMPRESSED
147 select HAVE_BLOCK_DEVICE
149 select OF_BOARD_SETUP
152 select SUPPORT_OF_CONTROL
153 select SYSRESET_CMD_POWEROFF
154 select SYS_CACHE_SHIFT_4
156 select SUPPORT_EXTENSION_SCAN
174 imply FUZZING_ENGINE_SANDBOX
181 imply PARTITION_TYPE_GUID
184 imply UDP_FUNCTION_FASTBOOT
197 imply ACPI_PMC_SANDBOX
207 imply GENERATE_ACPI_TABLE
211 bool "SuperH architecture"
212 select HAVE_PRIVATE_LIBGCC
213 select SUPPORT_OF_CONTROL
216 bool "x86 architecture"
219 select CREATE_ARCH_SYMLINK
221 select HAVE_ARCH_IOMAP
222 select HAVE_PRIVATE_LIBGCC
226 select SUPPORT_OF_CONTROL
227 select SYS_CACHE_SHIFT_6
229 select USE_PRIVATE_LIBGCC
232 imply HAS_ROM if X86_RESET_VECTOR
235 imply CMD_FPGA_LOADMK
259 imply USB_ETHER_SMSC95XX
264 imply ACPIGEN if !QEMU && !EFI_APP
265 imply SYSINFO if GENERATE_SMBIOS_TABLE
266 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
269 # Thing to enable for when SPL/TPL are enabled: SPL
272 imply SPL_DRIVERS_MISC
275 imply SPL_LIBCOMMON_SUPPORT
276 imply SPL_LIBGENERIC_SUPPORT
278 imply SPL_SPI_FLASH_SUPPORT
286 imply TPL_DRIVERS_MISC
289 imply TPL_LIBCOMMON_SUPPORT
290 imply TPL_LIBGENERIC_SUPPORT
298 bool "Xtensa architecture"
299 select CREATE_ARCH_SYMLINK
300 select SUPPORT_OF_CONTROL
307 This option should contain the architecture name to build the
308 appropriate arch/<CONFIG_SYS_ARCH> directory.
309 All the architectures should specify this option correctly.
314 This option should contain the CPU name to build the correct
315 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
317 This is optional. For those targets without the CPU directory,
318 leave this option empty.
323 This option should contain the SoC name to build the directory
324 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
326 This is optional. For those targets without the SoC directory,
327 leave this option empty.
332 This option should contain the vendor name of the target board.
334 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
335 directory is compiled.
336 If CONFIG_SYS_BOARD is also set, the sources under
337 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
339 This is optional. For those targets without the vendor directory,
340 leave this option empty.
345 This option should contain the name of the target board.
346 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
347 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
348 whether CONFIG_SYS_VENDOR is set or not.
350 This is optional. For those targets without the board directory,
351 leave this option empty.
353 config SYS_CONFIG_NAME
356 This option should contain the base name of board header file.
357 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
358 should be included from include/config.h.
360 config SYS_DISABLE_DCACHE_OPS
363 This option disables dcache flush and dcache invalidation
364 operations. For example, on coherent systems where cache
365 operatios are not required, enable this option to avoid them.
366 Note that, its up to the individual architectures to implement
370 hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
371 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
372 default 0xFF000000 if MPC8xx
373 default 0xF0000000 if ARCH_MPC8313
374 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
375 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
376 default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
377 ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
379 default SYS_CCSRBAR_DEFAULT
381 Address for the Internal Memory-Mapped Registers (IMMR) window used
382 to configure the features of many Freescale / NXP SoCs.
384 config SKIP_LOWLEVEL_INIT
385 bool "Skip the calls to certain low level initialization functions"
386 depends on ARM || MIPS || RISCV
388 If enabled, then certain low level initializations (like setting up
389 the memory controller) are omitted and/or U-Boot does not relocate
391 Normally this variable MUST NOT be defined. The only exception is
392 when U-Boot is loaded (to RAM) by some other boot loader or by a
393 debugger which performs these initializations itself.
395 config SPL_SKIP_LOWLEVEL_INIT
396 bool "Skip the calls to certain low level initialization functions"
397 depends on SPL && (ARM || MIPS || RISCV)
399 If enabled, then certain low level initializations (like setting up
400 the memory controller) are omitted and/or U-Boot does not relocate
402 Normally this variable MUST NOT be defined. The only exception is
403 when U-Boot is loaded (to RAM) by some other boot loader or by a
404 debugger which performs these initializations itself.
406 config TPL_SKIP_LOWLEVEL_INIT
407 bool "Skip the calls to certain low level initialization functions"
408 depends on SPL && ARM
410 If enabled, then certain low level initializations (like setting up
411 the memory controller) are omitted and/or U-Boot does not relocate
413 Normally this variable MUST NOT be defined. The only exception is
414 when U-Boot is loaded (to RAM) by some other boot loader or by a
415 debugger which performs these initializations itself.
417 config SKIP_LOWLEVEL_INIT_ONLY
418 bool "Skip the call to lowlevel_init during early boot ONLY"
421 This allows just the call to lowlevel_init() to be skipped. The
422 normal CP15 init (such as enabling the instruction cache) is still
425 config SPL_SKIP_LOWLEVEL_INIT_ONLY
426 bool "Skip the call to lowlevel_init during early boot ONLY"
427 depends on SPL && ARM
429 This allows just the call to lowlevel_init() to be skipped. The
430 normal CP15 init (such as enabling the instruction cache) is still
433 config TPL_SKIP_LOWLEVEL_INIT_ONLY
434 bool "Skip the call to lowlevel_init during early boot ONLY"
435 depends on TPL && ARM
437 This allows just the call to lowlevel_init() to be skipped. The
438 normal CP15 init (such as enabling the instruction cache) is still
441 source "arch/arc/Kconfig"
442 source "arch/arm/Kconfig"
443 source "arch/m68k/Kconfig"
444 source "arch/microblaze/Kconfig"
445 source "arch/mips/Kconfig"
446 source "arch/nios2/Kconfig"
447 source "arch/powerpc/Kconfig"
448 source "arch/sandbox/Kconfig"
449 source "arch/sh/Kconfig"
450 source "arch/x86/Kconfig"
451 source "arch/xtensa/Kconfig"
452 source "arch/riscv/Kconfig"
454 if ARM || M68K || PPC
456 source "arch/Kconfig.nxp"
460 source "board/keymile/Kconfig"
462 if MIPS || MICROBLAZE
465 prompt "Endianness selection"
467 Some MIPS boards can be configured for either little or big endian
468 byte order. These modes require different U-Boot images. In general there
469 is one preferred byteorder for a particular system but some systems are
470 just as commonly used in the one or the other endianness.
472 config SYS_BIG_ENDIAN
474 depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
476 config SYS_LITTLE_ENDIAN
478 depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE