2 * Copyright © 2014 Advanced Micro Devices, Inc.
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6 * copy of this software and associated documentation files (the "Software"),
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9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 #ifndef _AMDGPU_INTERNAL_H_
25 #define _AMDGPU_INTERNAL_H_
33 #include "xf86atomic.h"
35 #include "util_double_list.h"
37 #define AMDGPU_CS_MAX_RINGS 8
39 struct amdgpu_bo_va_hole {
40 struct list_head list;
45 struct amdgpu_bo_va_mgr {
46 /* the start virtual address */
48 struct list_head va_holes;
49 pthread_mutex_t bo_va_mutex;
50 uint32_t va_alignment;
53 struct amdgpu_device {
57 unsigned major_version;
58 unsigned minor_version;
60 /** List of buffer handles. Protected by bo_table_mutex. */
61 struct util_hash_table *bo_handles;
62 /** List of buffer GEM flink names. Protected by bo_table_mutex. */
63 struct util_hash_table *bo_flink_names;
64 /** List of buffer virtual memory ranges. Protected by bo_table_mutex. */
65 struct util_hash_table *bo_vas;
66 /** This protects all hash tables. */
67 pthread_mutex_t bo_table_mutex;
68 struct amdgpu_bo_va_mgr vamgr;
69 struct drm_amdgpu_info_device dev_info;
70 struct amdgpu_gpu_info info;
75 struct amdgpu_device *dev;
78 uint64_t virtual_mc_base_address;
83 pthread_mutex_t cpu_access_mutex;
89 * There are three mutexes.
90 * To avoid deadlock, only hold the mutexes in this order:
91 * sequence_mutex -> pendings_mutex -> pool_mutex.
93 struct amdgpu_context {
94 /** Mutex for accessing fences and to maintain command submissions
95 and pending lists in good sequence. */
96 pthread_mutex_t sequence_mutex;
97 /** Buffer for user fences */
98 struct amdgpu_ib *fence_ib;
99 /** The newest expired fence for the ring of the ip blocks. */
100 uint64_t expired_fences[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
101 /** Mutex for accessing pendings list. */
102 pthread_mutex_t pendings_mutex;
104 struct list_head pendings[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
105 /** Freed IBs not yet in pool */
106 struct list_head freed;
107 /** Mutex for accessing free ib pool. */
108 pthread_mutex_t pool_mutex;
109 /** Internal free IB pools. */
110 struct list_head ib_pools[AMDGPU_CS_IB_SIZE_NUM];
116 struct list_head list_node;
117 amdgpu_bo_handle buf_handle;
119 uint64_t virtual_mc_base_address;
120 enum amdgpu_cs_ib_size ib_size;
128 void amdgpu_device_free_internal(amdgpu_device_handle dev);
130 void amdgpu_bo_free_internal(amdgpu_bo_handle bo);
132 void amdgpu_vamgr_init(struct amdgpu_device *dev);
134 uint64_t amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr,
135 uint64_t size, uint64_t alignment);
137 void amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va,
140 int amdgpu_query_gpu_info_init(amdgpu_device_handle dev);
142 uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout);
149 * Increment src and decrement dst as if we were updating references
150 * for an assignment between 2 pointers of some objects.
152 * \return true if dst is 0
154 static inline bool update_references(atomic_t *dst, atomic_t *src)
159 assert(atomic_read(src) > 0);
163 assert(atomic_read(dst) > 0);
164 return atomic_dec_and_test(dst);
171 * Assignment between two amdgpu_bo pointers with reference counting.
174 * struct amdgpu_bo *dst = ... , *src = ...;
177 * // No reference counting. Only use this when you need to move
178 * // a reference from one pointer to another.
180 * amdgpu_bo_reference(&dst, src);
181 * // Reference counters are updated. dst is decremented and src is
182 * // incremented. dst is freed if its reference counter is 0.
184 static inline void amdgpu_bo_reference(struct amdgpu_bo **dst,
185 struct amdgpu_bo *src)
187 if (update_references(&(*dst)->refcount, &src->refcount))
188 amdgpu_bo_free_internal(*dst);
193 * Assignment between two amdgpu_device pointers with reference counting.
196 * struct amdgpu_device *dst = ... , *src = ...;
199 * // No reference counting. Only use this when you need to move
200 * // a reference from one pointer to another.
202 * amdgpu_device_reference(&dst, src);
203 * // Reference counters are updated. dst is decremented and src is
204 * // incremented. dst is freed if its reference counter is 0.
206 void amdgpu_device_reference(struct amdgpu_device **dst,
207 struct amdgpu_device *src);