amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 /**
  25  * \file amdgpu_device.c
  26  *
  27  *  Implementation of functions for AMD GPU device
  28  *
  29  */
  30
  31 #ifdef HAVE_CONFIG_H
  32 #include "config.h"
  33 #endif
  34
  35 #include <sys/stat.h>
  36 #include <errno.h>
  37 #include <string.h>
  38 #include <stdio.h>
  39 #include <stdlib.h>
  40 #include <unistd.h>
  41
  42 #include "xf86drm.h"
  43 #include "amdgpu_drm.h"
  44 #include "amdgpu_internal.h"
  45 #include "util_hash_table.h"
  46 #include "util_math.h"
  47
  48 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
  49 #define UINT_TO_PTR(x) ((void *)((intptr_t)(x)))
  50
  51 static pthread_mutex_t fd_mutex = PTHREAD_MUTEX_INITIALIZER;
  52 static struct util_hash_table *fd_tab;
  53
  54 static unsigned handle_hash(void *key)
  55 {
  56         return PTR_TO_UINT(key);
  57 }
  58
  59 static int handle_compare(void *key1, void *key2)
  60 {
  61         return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
  62 }
  63
  64 static unsigned fd_hash(void *key)
  65 {
  66         int fd = PTR_TO_UINT(key);
  67         char *name = drmGetPrimaryDeviceNameFromFd(fd);
  68         unsigned result = 0;
  69         char *c;
  70
  71         if (name == NULL)
  72                 return 0;
  73
  74         for (c = name; *c; ++c)
  75                 result += *c;
  76
  77         free(name);
  78
  79         return result;
  80 }
  81
  82 static int fd_compare(void *key1, void *key2)
  83 {
  84         int fd1 = PTR_TO_UINT(key1);
  85         int fd2 = PTR_TO_UINT(key2);
  86         char *name1 = drmGetPrimaryDeviceNameFromFd(fd1);
  87         char *name2 = drmGetPrimaryDeviceNameFromFd(fd2);
  88         int result;
  89
  90         if (name1 == NULL || name2 == NULL) {
  91                 free(name1);
  92                 free(name2);
  93                 return 0;
  94         }
  95
  96         result = strcmp(name1, name2);
  97         free(name1);
  98         free(name2);
  99
 100         return result;
 101 }
 102
 103 /**
 104 * Get the authenticated form fd,
 105 *
 106 * \param   fd   - \c [in]  File descriptor for AMD GPU device
 107 * \param   auth - \c [out] Pointer to output the fd is authenticated or not
 108 *                          A render node fd, output auth = 0
 109 *                          A legacy fd, get the authenticated for compatibility root
 110 *
 111 * \return   0 on success\n
 112 *          >0 - AMD specific error code\n
 113 *          <0 - Negative POSIX Error code
 114 */
 115 static int amdgpu_get_auth(int fd, int *auth)
 116 {
 117         int r = 0;
 118         drm_client_t client = {};
 119
 120         if (drmGetNodeTypeFromFd(fd) == DRM_NODE_RENDER)
 121                 *auth = 0;
 122         else {
 123                 client.idx = 0;
 124                 r = drmIoctl(fd, DRM_IOCTL_GET_CLIENT, &client);
 125                 if (!r)
 126                         *auth = client.auth;
 127         }
 128         return r;
 129 }
 130
 131 static void amdgpu_device_free_internal(amdgpu_device_handle dev)
 132 {
 133         amdgpu_vamgr_deinit(&dev->vamgr_32);
 134         amdgpu_vamgr_deinit(&dev->vamgr);
 135         util_hash_table_destroy(dev->bo_flink_names);
 136         util_hash_table_destroy(dev->bo_handles);
 137         pthread_mutex_destroy(&dev->bo_table_mutex);
 138         util_hash_table_remove(fd_tab, UINT_TO_PTR(dev->fd));
 139         close(dev->fd);
 140         if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd))
 141                 close(dev->flink_fd);
 142         free(dev->marketing_name);
 143         free(dev);
 144 }
 145
 146 /**
 147  * Assignment between two amdgpu_device pointers with reference counting.
 148  *
 149  * Usage:
 150  *    struct amdgpu_device *dst = ... , *src = ...;
 151  *
 152  *    dst = src;
 153  *    // No reference counting. Only use this when you need to move
 154  *    // a reference from one pointer to another.
 155  *
 156  *    amdgpu_device_reference(&dst, src);
 157  *    // Reference counters are updated. dst is decremented and src is
 158  *    // incremented. dst is freed if its reference counter is 0.
 159  */
 160 static void amdgpu_device_reference(struct amdgpu_device **dst,
 161                              struct amdgpu_device *src)
 162 {
 163         if (update_references(&(*dst)->refcount, &src->refcount))
 164                 amdgpu_device_free_internal(*dst);
 165         *dst = src;
 166 }
 167
 168 int amdgpu_device_initialize(int fd,
 169                              uint32_t *major_version,
 170                              uint32_t *minor_version,
 171                              amdgpu_device_handle *device_handle)
 172 {
 173         struct amdgpu_device *dev;
 174         drmVersionPtr version;
 175         int r;
 176         int flag_auth = 0;
 177         int flag_authexist=0;
 178         uint32_t accel_working = 0;
 179         uint64_t start, max;
 180
 181         *device_handle = NULL;
 182
 183         pthread_mutex_lock(&fd_mutex);
 184         if (!fd_tab)
 185                 fd_tab = util_hash_table_create(fd_hash, fd_compare);
 186         r = amdgpu_get_auth(fd, &flag_auth);
 187         if (r) {
 188                 fprintf(stderr, "%s: amdgpu_get_auth (1) failed (%i)\n",
 189                         __func__, r);
 190                 pthread_mutex_unlock(&fd_mutex);
 191                 return r;
 192         }
 193         dev = util_hash_table_get(fd_tab, UINT_TO_PTR(fd));
 194         if (dev) {
 195                 r = amdgpu_get_auth(dev->fd, &flag_authexist);
 196                 if (r) {
 197                         fprintf(stderr, "%s: amdgpu_get_auth (2) failed (%i)\n",
 198                                 __func__, r);
 199                         pthread_mutex_unlock(&fd_mutex);
 200                         return r;
 201                 }
 202                 if ((flag_auth) && (!flag_authexist)) {
 203                         dev->flink_fd = dup(fd);
 204                 }
 205                 *major_version = dev->major_version;
 206                 *minor_version = dev->minor_version;
 207                 amdgpu_device_reference(device_handle, dev);
 208                 pthread_mutex_unlock(&fd_mutex);
 209                 return 0;
 210         }
 211
 212         dev = calloc(1, sizeof(struct amdgpu_device));
 213         if (!dev) {
 214                 fprintf(stderr, "%s: calloc failed\n", __func__);
 215                 pthread_mutex_unlock(&fd_mutex);
 216                 return -ENOMEM;
 217         }
 218
 219         dev->fd = -1;
 220         dev->flink_fd = -1;
 221
 222         atomic_set(&dev->refcount, 1);
 223
 224         version = drmGetVersion(fd);
 225         if (version->version_major != 3) {
 226                 fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 227                         "only compatible with 3.x.x.\n",
 228                         __func__,
 229                         version->version_major,
 230                         version->version_minor,
 231                         version->version_patchlevel);
 232                 drmFreeVersion(version);
 233                 r = -EBADF;
 234                 goto cleanup;
 235         }
 236
 237         dev->fd = dup(fd);
 238         dev->flink_fd = dev->fd;
 239         dev->major_version = version->version_major;
 240         dev->minor_version = version->version_minor;
 241         drmFreeVersion(version);
 242
 243         dev->bo_flink_names = util_hash_table_create(handle_hash,
 244                                                      handle_compare);
 245         dev->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 246         pthread_mutex_init(&dev->bo_table_mutex, NULL);
 247
 248         /* Check if acceleration is working. */
 249         r = amdgpu_query_info(dev, AMDGPU_INFO_ACCEL_WORKING, 4, &accel_working);
 250         if (r) {
 251                 fprintf(stderr, "%s: amdgpu_query_info(ACCEL_WORKING) failed (%i)\n",
 252                         __func__, r);
 253                 goto cleanup;
 254         }
 255         if (!accel_working) {
 256                 fprintf(stderr, "%s: AMDGPU_INFO_ACCEL_WORKING = 0\n", __func__);
 257                 r = -EBADF;
 258                 goto cleanup;
 259         }
 260
 261         r = amdgpu_query_gpu_info_init(dev);
 262         if (r) {
 263                 fprintf(stderr, "%s: amdgpu_query_gpu_info_init failed\n", __func__);
 264                 goto cleanup;
 265         }
 266
 267         if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max) {
 268                 start = dev->dev_info.high_va_offset;
 269                 max = dev->dev_info.high_va_max;
 270         } else {
 271                 start = dev->dev_info.virtual_address_offset;
 272                 max = dev->dev_info.virtual_address_max;
 273         }
 274
 275         max = MIN2(max, (start & ~0xffffffffULL) + 0x100000000ULL);
 276         amdgpu_vamgr_init(&dev->vamgr_32, start, max,
 277                           dev->dev_info.virtual_address_alignment);
 278         dev->address32_hi = start >> 32;
 279
 280         start = max;
 281         if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max)
 282                 max = dev->dev_info.high_va_max;
 283         else
 284                 max = dev->dev_info.virtual_address_max;
 285         amdgpu_vamgr_init(&dev->vamgr, start, max,
 286                           dev->dev_info.virtual_address_alignment);
 287
 288         amdgpu_parse_asic_ids(dev);
 289
 290         *major_version = dev->major_version;
 291         *minor_version = dev->minor_version;
 292         *device_handle = dev;
 293         util_hash_table_set(fd_tab, UINT_TO_PTR(dev->fd), dev);
 294         pthread_mutex_unlock(&fd_mutex);
 295
 296         return 0;
 297
 298 cleanup:
 299         if (dev->fd >= 0)
 300                 close(dev->fd);
 301         free(dev);
 302         pthread_mutex_unlock(&fd_mutex);
 303         return r;
 304 }
 305
 306 int amdgpu_device_deinitialize(amdgpu_device_handle dev)
 307 {
 308         amdgpu_device_reference(&dev, NULL);
 309         return 0;
 310 }
 311
 312 const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
 313 {
 314         return dev->marketing_name;
 315 }
 316
 317 int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info,
 318                          void *value)
 319 {
 320         uint32_t *val32 = (uint32_t*)value;
 321
 322         switch (info) {
 323         case amdgpu_sw_info_address32_hi:
 324                 *val32 = dev->address32_hi;
 325                 return 0;
 326         }
 327         return -EINVAL;
 328 }