amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22 */
  23 #include <stdlib.h>
  24 #include <stdio.h>
  25 #include <string.h>
  26 #include <errno.h>
  27 #include <pthread.h>
  28 #include <sched.h>
  29 #include <sys/ioctl.h>
  30
  31 #include "xf86drm.h"
  32 #include "amdgpu_drm.h"
  33 #include "amdgpu_internal.h"
  34
  35 /**
  36  * Create command submission context
  37  *
  38  * \param   dev - \c [in] amdgpu device handle
  39  * \param   context - \c [out] amdgpu context handle
  40  *
  41  * \return  0 on success otherwise POSIX Error code
  42 */
  43 int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
  44                          amdgpu_context_handle *context)
  45 {
  46         struct amdgpu_bo_alloc_request alloc_buffer = {};
  47         struct amdgpu_bo_alloc_result info = {};
  48         struct amdgpu_context *gpu_context;
  49         union drm_amdgpu_ctx args;
  50         int r;
  51
  52         if (NULL == dev)
  53                 return -EINVAL;
  54         if (NULL == context)
  55                 return -EINVAL;
  56
  57         gpu_context = calloc(1, sizeof(struct amdgpu_context));
  58         if (NULL == gpu_context)
  59                 return -ENOMEM;
  60
  61         gpu_context->dev = dev;
  62
  63         r = pthread_mutex_init(&gpu_context->sequence_mutex, NULL);
  64         if (r)
  65                 goto error_mutex;
  66
  67         /* Create the fence BO */
  68         alloc_buffer.alloc_size = 4 * 1024;
  69         alloc_buffer.phys_alignment = 4 * 1024;
  70         alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
  71
  72         r = amdgpu_bo_alloc(dev, &alloc_buffer, &info);
  73         if (r)
  74                 goto error_fence_alloc;
  75         gpu_context->fence_bo = info.buf_handle;
  76
  77         r = amdgpu_bo_cpu_map(gpu_context->fence_bo, &gpu_context->fence_cpu);
  78         if (r)
  79                 goto error_fence_map;
  80
  81         /* Create the context */
  82         memset(&args, 0, sizeof(args));
  83         args.in.op = AMDGPU_CTX_OP_ALLOC_CTX;
  84         r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args));
  85         if (r)
  86                 goto error_kernel;
  87
  88         gpu_context->id = args.out.alloc.ctx_id;
  89         *context = (amdgpu_context_handle)gpu_context;
  90
  91         return 0;
  92
  93 error_kernel:
  94         amdgpu_bo_cpu_unmap(gpu_context->fence_bo);
  95
  96 error_fence_map:
  97         amdgpu_bo_free(gpu_context->fence_bo);
  98
  99 error_fence_alloc:
 100         pthread_mutex_destroy(&gpu_context->sequence_mutex);
 101
 102 error_mutex:
 103         free(gpu_context);
 104         return r;
 105 }
 106
 107 /**
 108  * Release command submission context
 109  *
 110  * \param   dev - \c [in] amdgpu device handle
 111  * \param   context - \c [in] amdgpu context handle
 112  *
 113  * \return  0 on success otherwise POSIX Error code
 114 */
 115 int amdgpu_cs_ctx_free(amdgpu_context_handle context)
 116 {
 117         union drm_amdgpu_ctx args;
 118         int r;
 119
 120         if (NULL == context)
 121                 return -EINVAL;
 122
 123         r = amdgpu_bo_cpu_unmap(context->fence_bo);
 124         if (r)
 125                 return r;
 126
 127         r = amdgpu_bo_free(context->fence_bo);
 128         if (r)
 129                 return r;
 130
 131         pthread_mutex_destroy(&context->sequence_mutex);
 132
 133         /* now deal with kernel side */
 134         memset(&args, 0, sizeof(args));
 135         args.in.op = AMDGPU_CTX_OP_FREE_CTX;
 136         args.in.ctx_id = context->id;
 137         r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
 138                                 &args, sizeof(args));
 139
 140         free(context);
 141
 142         return r;
 143 }
 144
 145 int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
 146                                 uint32_t *state, uint32_t *hangs)
 147 {
 148         union drm_amdgpu_ctx args;
 149         int r;
 150
 151         if (!context)
 152                 return -EINVAL;
 153
 154         memset(&args, 0, sizeof(args));
 155         args.in.op = AMDGPU_CTX_OP_QUERY_STATE;
 156         args.in.ctx_id = context->id;
 157         r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
 158                                 &args, sizeof(args));
 159         if (!r) {
 160                 *state = args.out.state.reset_status;
 161                 *hangs = args.out.state.hangs;
 162         }
 163         return r;
 164 }
 165
 166 static uint32_t amdgpu_cs_fence_index(unsigned ip, unsigned ring)
 167 {
 168         return ip * AMDGPU_CS_MAX_RINGS + ring;
 169 }
 170
 171 /**
 172  * Submit command to kernel DRM
 173  * \param   dev - \c [in]  Device handle
 174  * \param   context - \c [in]  GPU Context
 175  * \param   ibs_request - \c [in]  Pointer to submission requests
 176  * \param   fence - \c [out] return fence for this submission
 177  *
 178  * \return  0 on success otherwise POSIX Error code
 179  * \sa amdgpu_cs_submit()
 180 */
 181 static int amdgpu_cs_submit_one(amdgpu_context_handle context,
 182                                 struct amdgpu_cs_request *ibs_request,
 183                                 uint64_t *fence)
 184 {
 185         int r = 0;
 186         uint32_t i, size;
 187         union drm_amdgpu_cs cs;
 188         uint64_t *chunk_array;
 189         struct drm_amdgpu_cs_chunk *chunks;
 190         struct drm_amdgpu_cs_chunk_data *chunk_data;
 191
 192         if (ibs_request->ip_type >= AMDGPU_HW_IP_NUM)
 193                 return -EINVAL;
 194         if (ibs_request->ring >= AMDGPU_CS_MAX_RINGS)
 195                 return -EINVAL;
 196         if (ibs_request->number_of_ibs > AMDGPU_CS_MAX_IBS_PER_SUBMIT)
 197                 return -EINVAL;
 198
 199         size = (ibs_request->number_of_ibs + 1) * (
 200                 sizeof(uint64_t) +
 201                 sizeof(struct drm_amdgpu_cs_chunk) +
 202                 sizeof(struct drm_amdgpu_cs_chunk_data));
 203
 204         chunk_array = calloc(1, size);
 205         if (NULL == chunk_array)
 206                 return -ENOMEM;
 207
 208         chunks = (struct drm_amdgpu_cs_chunk *)(chunk_array + ibs_request->number_of_ibs + 1);
 209         chunk_data = (struct drm_amdgpu_cs_chunk_data *)(chunks + ibs_request->number_of_ibs + 1);
 210
 211         memset(&cs, 0, sizeof(cs));
 212         cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
 213         cs.in.ctx_id = context->id;
 214         if (ibs_request->resources)
 215                 cs.in.bo_list_handle = ibs_request->resources->handle;
 216         cs.in.num_chunks = ibs_request->number_of_ibs;
 217         /* IB chunks */
 218         for (i = 0; i < ibs_request->number_of_ibs; i++) {
 219                 struct amdgpu_cs_ib_info *ib;
 220                 chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
 221                 chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
 222                 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
 223                 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
 224
 225                 ib = &ibs_request->ibs[i];
 226
 227                 chunk_data[i].ib_data._pad = 0;
 228                 chunk_data[i].ib_data.va_start = ib->ib_mc_address;
 229                 chunk_data[i].ib_data.ib_bytes = ib->size * 4;
 230                 chunk_data[i].ib_data.ip_type = ibs_request->ip_type;
 231                 chunk_data[i].ib_data.ip_instance = ibs_request->ip_instance;
 232                 chunk_data[i].ib_data.ring = ibs_request->ring;
 233                 chunk_data[i].ib_data.flags = ib->flags;
 234         }
 235
 236         pthread_mutex_lock(&context->sequence_mutex);
 237
 238         if (ibs_request->ip_type != AMDGPU_HW_IP_UVD &&
 239             ibs_request->ip_type != AMDGPU_HW_IP_VCE) {
 240                 i = cs.in.num_chunks++;
 241
 242                 /* fence chunk */
 243                 chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
 244                 chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
 245                 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
 246                 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
 247
 248                 /* fence bo handle */
 249                 chunk_data[i].fence_data.handle = context->fence_bo->handle;
 250                 /* offset */
 251                 chunk_data[i].fence_data.offset = amdgpu_cs_fence_index(
 252                         ibs_request->ip_type, ibs_request->ring);
 253                 chunk_data[i].fence_data.offset *= sizeof(uint64_t);
 254         }
 255
 256         r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CS,
 257                                 &cs, sizeof(cs));
 258         if (r)
 259                 goto error_unlock;
 260
 261         *fence = cs.out.handle;
 262
 263 error_unlock:
 264         pthread_mutex_unlock(&context->sequence_mutex);
 265         free(chunk_array);
 266         return r;
 267 }
 268
 269 int amdgpu_cs_submit(amdgpu_context_handle context,
 270                      uint64_t flags,
 271                      struct amdgpu_cs_request *ibs_request,
 272                      uint32_t number_of_requests,
 273                      uint64_t *fences)
 274 {
 275         uint32_t i;
 276         int r;
 277
 278         if (NULL == context)
 279                 return -EINVAL;
 280         if (NULL == ibs_request)
 281                 return -EINVAL;
 282         if (NULL == fences)
 283                 return -EINVAL;
 284
 285         r = 0;
 286         for (i = 0; i < number_of_requests; i++) {
 287                 r = amdgpu_cs_submit_one(context, ibs_request, fences);
 288                 if (r)
 289                         break;
 290                 fences++;
 291                 ibs_request++;
 292         }
 293
 294         return r;
 295 }
 296
 297 /**
 298  * Calculate absolute timeout.
 299  *
 300  * \param   timeout - \c [in] timeout in nanoseconds.
 301  *
 302  * \return  absolute timeout in nanoseconds
 303 */
 304 uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout)
 305 {
 306         int r;
 307
 308         if (timeout != AMDGPU_TIMEOUT_INFINITE) {
 309                 struct timespec current;
 310                 r = clock_gettime(CLOCK_MONOTONIC, &current);
 311                 if (r)
 312                         return r;
 313
 314                 timeout += ((uint64_t)current.tv_sec) * 1000000000ull;
 315                 timeout += current.tv_nsec;
 316         }
 317         return timeout;
 318 }
 319
 320 static int amdgpu_ioctl_wait_cs(amdgpu_context_handle context,
 321                                 unsigned ip,
 322                                 unsigned ip_instance,
 323                                 uint32_t ring,
 324                                 uint64_t handle,
 325                                 uint64_t timeout_ns,
 326                                 bool *busy)
 327 {
 328         amdgpu_device_handle dev = context->dev;
 329         union drm_amdgpu_wait_cs args;
 330         int r;
 331
 332         memset(&args, 0, sizeof(args));
 333         args.in.handle = handle;
 334         args.in.ip_type = ip;
 335         args.in.ip_instance = ip_instance;
 336         args.in.ring = ring;
 337         args.in.timeout = amdgpu_cs_calculate_timeout(timeout_ns);
 338         args.in.ctx_id = context->id;
 339
 340         /* Handle errors manually here because of timeout */
 341         r = ioctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_CS, &args);
 342         if (r == -1 && (errno == EINTR || errno == EAGAIN)) {
 343                 *busy = true;
 344                 return 0;
 345         } else if (r)
 346                 return -errno;
 347
 348         *busy = args.out.status;
 349         return 0;
 350 }
 351
 352 int amdgpu_cs_query_fence_status(struct amdgpu_cs_query_fence *fence,
 353                                  uint32_t *expired)
 354 {
 355         amdgpu_context_handle context;
 356         uint64_t *signaled_fence;
 357         uint64_t *expired_fence;
 358         unsigned ip_type, ip_instance;
 359         uint32_t ring;
 360         bool busy = true;
 361         int r;
 362
 363         if (NULL == fence)
 364                 return -EINVAL;
 365         if (NULL == expired)
 366                 return -EINVAL;
 367         if (NULL == fence->context)
 368                 return -EINVAL;
 369         if (fence->ip_type >= AMDGPU_HW_IP_NUM)
 370                 return -EINVAL;
 371         if (fence->ring >= AMDGPU_CS_MAX_RINGS)
 372                 return -EINVAL;
 373
 374         context = fence->context;
 375         ip_type = fence->ip_type;
 376         ip_instance = fence->ip_instance;
 377         ring = fence->ring;
 378         signaled_fence = context->fence_cpu;
 379         signaled_fence += amdgpu_cs_fence_index(ip_type, ring);
 380         expired_fence = &context->expired_fences[ip_type][ip_instance][ring];
 381         *expired = false;
 382
 383         pthread_mutex_lock(&context->sequence_mutex);
 384         if (fence->fence <= *expired_fence) {
 385                 /* This fence value is expired already. */
 386                 pthread_mutex_unlock(&context->sequence_mutex);
 387                 *expired = true;
 388                 return 0;
 389         }
 390
 391         if (fence->fence <= *signaled_fence) {
 392                 /* This fence value is signaled already. */
 393                 *expired_fence = *signaled_fence;
 394                 pthread_mutex_unlock(&context->sequence_mutex);
 395                 *expired = true;
 396                 return 0;
 397         }
 398
 399         if (fence->timeout_ns == 0) {
 400                 pthread_mutex_unlock(&context->sequence_mutex);
 401                 return 0;
 402         }
 403
 404         pthread_mutex_unlock(&context->sequence_mutex);
 405
 406         r = amdgpu_ioctl_wait_cs(context, ip_type, ip_instance, ring,
 407                                  fence->fence, fence->timeout_ns, &busy);
 408         if (!r && !busy) {
 409                 *expired = true;
 410                 pthread_mutex_lock(&context->sequence_mutex);
 411                 /* The thread doesn't hold sequence_mutex. Other thread could
 412                    update *expired_fence already. Check whether there is a
 413                    newerly expired fence. */
 414                 if (fence->fence > *expired_fence)
 415                         *expired_fence = fence->fence;
 416                 pthread_mutex_unlock(&context->sequence_mutex);
 417         }
 418
 419         return r;
 420 }
 421