2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 * Declare public libdrm_amdgpu API
29 * This file define API exposed by libdrm_amdgpu library.
30 * User wanted to use libdrm_amdgpu functionality must include
40 struct drm_amdgpu_info_hw_ip;
42 /*--------------------------------------------------------------------------*/
43 /* --------------------------- Defines ------------------------------------ */
44 /*--------------------------------------------------------------------------*/
47 * Define max. number of Command Buffers (IB) which could be sent to the single
48 * hardware IP to accommodate CE/DE requirements
50 * \sa amdgpu_cs_ib_info
52 #define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4
57 #define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull
60 /*--------------------------------------------------------------------------*/
61 /* ----------------------------- Enums ------------------------------------ */
62 /*--------------------------------------------------------------------------*/
65 * Enum describing possible handle types
67 * \sa amdgpu_bo_import, amdgpu_bo_export
70 enum amdgpu_bo_handle_type {
71 /** GEM flink name (needs DRM authentication, used by DRI2) */
72 amdgpu_bo_handle_type_gem_flink_name = 0,
74 /** KMS handle which is used by all driver ioctls */
75 amdgpu_bo_handle_type_kms = 1,
77 /** DMA-buf fd handle */
78 amdgpu_bo_handle_type_dma_buf_fd = 2
82 /*--------------------------------------------------------------------------*/
83 /* -------------------------- Datatypes ----------------------------------- */
84 /*--------------------------------------------------------------------------*/
87 * Define opaque pointer to context associated with fd.
88 * This context will be returned as the result of
89 * "initialize" function and should be pass as the first
90 * parameter to any API call
92 typedef struct amdgpu_device *amdgpu_device_handle;
95 * Define GPU Context type as pointer to opaque structure
96 * Example of GPU Context is the "rendering" context associated
97 * with OpenGL context (glCreateContext)
99 typedef struct amdgpu_context *amdgpu_context_handle;
102 * Define handle for amdgpu resources: buffer, GDS, etc.
104 typedef struct amdgpu_bo *amdgpu_bo_handle;
107 * Define handle for list of BOs
109 typedef struct amdgpu_bo_list *amdgpu_bo_list_handle;
112 /*--------------------------------------------------------------------------*/
113 /* -------------------------- Structures ---------------------------------- */
114 /*--------------------------------------------------------------------------*/
117 * Structure describing memory allocation request
119 * \sa amdgpu_bo_alloc()
122 struct amdgpu_bo_alloc_request {
123 /** Allocation request. It must be aligned correctly. */
127 * It may be required to have some specific alignment requirements
128 * for physical back-up storage (e.g. for displayable surface).
129 * If 0 there is no special alignment requirement
131 uint64_t phys_alignment;
134 * UMD should specify where to allocate memory and how it
135 * will be accessed by the CPU.
137 uint32_t preferred_heap;
139 /** Additional flags passed on allocation */
144 * Structure describing memory allocation request
146 * \sa amdgpu_bo_alloc()
148 struct amdgpu_bo_alloc_result {
149 /** Assigned virtual MC Base Address */
150 uint64_t virtual_mc_base_address;
152 /** Handle of allocated memory to be used by the given process only. */
153 amdgpu_bo_handle buf_handle;
157 * Special UMD specific information associated with buffer.
159 * It may be need to pass some buffer charactersitic as part
160 * of buffer sharing. Such information are defined UMD and
161 * opaque for libdrm_amdgpu as well for kernel driver.
163 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info,
164 * amdgpu_bo_import(), amdgpu_bo_export
167 struct amdgpu_bo_metadata {
168 /** Special flag associated with surface */
172 * ASIC-specific tiling information (also used by DCE).
173 * The encoding is defined by the AMDGPU_TILING_* definitions.
175 uint64_t tiling_info;
177 /** Size of metadata associated with the buffer, in bytes. */
178 uint32_t size_metadata;
180 /** UMD specific metadata. Opaque for kernel */
181 uint32_t umd_metadata[64];
185 * Structure describing allocated buffer. Client may need
186 * to query such information as part of 'sharing' buffers mechanism
188 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info(),
189 * amdgpu_bo_import(), amdgpu_bo_export()
191 struct amdgpu_bo_info {
192 /** Allocated memory size */
196 * It may be required to have some specific alignment requirements
197 * for physical back-up storage.
199 uint64_t phys_alignment;
202 * Assigned virtual MC Base Address.
203 * \note This information will be returned only if this buffer was
204 * allocated in the same process otherwise 0 will be returned.
206 uint64_t virtual_mc_base_address;
208 /** Heap where to allocate memory. */
209 uint32_t preferred_heap;
211 /** Additional allocation flags. */
212 uint64_t alloc_flags;
214 /** Metadata associated with buffer if any. */
215 struct amdgpu_bo_metadata metadata;
219 * Structure with information about "imported" buffer
221 * \sa amdgpu_bo_import()
224 struct amdgpu_bo_import_result {
225 /** Handle of memory/buffer to use */
226 amdgpu_bo_handle buf_handle;
231 /** Assigned virtual MC Base Address */
232 uint64_t virtual_mc_base_address;
238 * Structure to describe GDS partitioning information.
239 * \note OA and GWS resources are asscoiated with GDS partition
241 * \sa amdgpu_gpu_resource_query_gds_info
244 struct amdgpu_gds_resource_info {
245 uint32_t gds_gfx_partition_size;
246 uint32_t compute_partition_size;
247 uint32_t gds_total_size;
248 uint32_t gws_per_gfx_partition;
249 uint32_t gws_per_compute_partition;
250 uint32_t oa_per_gfx_partition;
251 uint32_t oa_per_compute_partition;
255 * Structure describing CS dependency
257 * \sa amdgpu_cs_request, amdgpu_cs_submit()
260 struct amdgpu_cs_dep_info {
261 /** Context to which the fence belongs */
262 amdgpu_context_handle context;
264 /** To which HW IP type the fence belongs */
267 /** IP instance index if there are several IPs of the same type. */
268 uint32_t ip_instance;
270 /** Ring index of the HW IP */
273 /** Specify fence for which we need to check
274 * submission status.*/
279 * Structure describing IB
281 * \sa amdgpu_cs_request, amdgpu_cs_submit()
284 struct amdgpu_cs_ib_info {
288 /** Virtual MC address of the command buffer */
289 uint64_t ib_mc_address;
292 * Size of Command Buffer to be submitted.
293 * - The size is in units of dwords (4 bytes).
294 * - Must be less or equal to the size of allocated IB
301 * Structure describing submission request
303 * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx
305 * \sa amdgpu_cs_submit()
307 struct amdgpu_cs_request {
308 /** Specify flags with additional information */
311 /** Specify HW IP block type to which to send the IB. */
314 /** IP instance index if there are several IPs of the same type. */
315 unsigned ip_instance;
318 * Specify ring index of the IP. We could have several rings
319 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1.
324 * List handle with resources used by this request.
326 amdgpu_bo_list_handle resources;
329 * Number of dependencies this Command submission needs to
330 * wait for before starting execution.
332 uint32_t number_of_dependencies;
335 * Array of dependencies which need to be met before
336 * execution can start.
338 struct amdgpu_cs_dep_info *dependencies;
340 /** Number of IBs to submit in the field ibs. */
341 uint32_t number_of_ibs;
344 * IBs to submit. Those IBs will be submit together as single entity
346 struct amdgpu_cs_ib_info *ibs;
350 * Structure describing request to check submission state using fence
352 * \sa amdgpu_cs_query_fence_status()
355 struct amdgpu_cs_query_fence {
357 /** In which context IB was sent to execution */
358 amdgpu_context_handle context;
360 /** Timeout in nanoseconds. */
363 /** To which HW IP type the fence belongs */
366 /** IP instance index if there are several IPs of the same type. */
367 unsigned ip_instance;
369 /** Ring index of the HW IP */
375 /** Specify fence for which we need to check
376 * submission status.*/
381 * Structure which provide information about GPU VM MC Address space
382 * alignments requirements
384 * \sa amdgpu_query_buffer_size_alignment
386 struct amdgpu_buffer_size_alignments {
387 /** Size alignment requirement for allocation in
392 * Size alignment requirement for allocation in remote memory
394 uint64_t size_remote;
399 * Structure which provide information about heap
401 * \sa amdgpu_query_heap_info()
404 struct amdgpu_heap_info {
405 /** Theoretical max. available memory in the given heap */
409 * Number of bytes allocated in the heap. This includes all processes
410 * and private allocations in the kernel. It changes when new buffers
411 * are allocated, freed, and moved. It cannot be larger than
417 * Theoretical possible max. size of buffer which
418 * could be allocated in the given heap
420 uint64_t max_allocation;
426 * Describe GPU h/w info needed for UMD correct initialization
428 * \sa amdgpu_query_gpu_info()
430 struct amdgpu_gpu_info {
433 /**< Chip revision */
435 /** Chip external revision */
436 uint32_t chip_external_rev;
441 /** max engine clock*/
442 uint64_t max_engine_clk;
443 /** max memory clock */
444 uint64_t max_memory_clk;
445 /** number of shader engines */
446 uint32_t num_shader_engines;
447 /** number of shader arrays per engine */
448 uint32_t num_shader_arrays_per_engine;
449 /** Number of available good shader pipes */
450 uint32_t avail_quad_shader_pipes;
451 /** Max. number of shader pipes.(including good and bad pipes */
452 uint32_t max_quad_shader_pipes;
453 /** Number of parameter cache entries per shader quad pipe */
454 uint32_t cache_entries_per_quad_pipe;
455 /** Number of available graphics context */
456 uint32_t num_hw_gfx_contexts;
457 /** Number of render backend pipes */
459 /** Enabled render backend pipe mask */
460 uint32_t enabled_rb_pipes_mask;
461 /** Frequency of GPU Counter */
462 uint32_t gpu_counter_freq;
463 /** CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE */
464 uint32_t backend_disable[4];
465 /** Value of MC_ARB_RAMCFG register*/
466 uint32_t mc_arb_ramcfg;
467 /** Value of GB_ADDR_CONFIG */
468 uint32_t gb_addr_cfg;
469 /** Values of the GB_TILE_MODE0..31 registers */
470 uint32_t gb_tile_mode[32];
471 /** Values of GB_MACROTILE_MODE0..15 registers */
472 uint32_t gb_macro_tile_mode[16];
473 /** Value of PA_SC_RASTER_CONFIG register per SE */
474 uint32_t pa_sc_raster_cfg[4];
475 /** Value of PA_SC_RASTER_CONFIG_1 register per SE */
476 uint32_t pa_sc_raster_cfg1[4];
478 uint32_t cu_active_number;
480 uint32_t cu_bitmap[4][4];
481 /* video memory type info*/
483 /* video memory bit width*/
484 uint32_t vram_bit_width;
485 /** constant engine ram size*/
486 uint32_t ce_ram_size;
490 /*--------------------------------------------------------------------------*/
491 /*------------------------- Functions --------------------------------------*/
492 /*--------------------------------------------------------------------------*/
495 * Initialization / Cleanup
502 * \param fd - \c [in] File descriptor for AMD GPU device
503 * received previously as the result of
504 * e.g. drmOpen() call.
505 * For legacy fd type, the DRI2/DRI3 authentication
506 * should be done before calling this function.
507 * \param major_version - \c [out] Major version of library. It is assumed
508 * that adding new functionality will cause
509 * increase in major version
510 * \param minor_version - \c [out] Minor version of library
511 * \param device_handle - \c [out] Pointer to opaque context which should
512 * be passed as the first parameter on each
516 * \return 0 on success\n
517 * >0 - AMD specific error code\n
518 * <0 - Negative POSIX Error code
521 * \sa amdgpu_device_deinitialize()
523 int amdgpu_device_initialize(int fd,
524 uint32_t *major_version,
525 uint32_t *minor_version,
526 amdgpu_device_handle *device_handle);
532 * When access to such library does not needed any more the special
533 * function must be call giving opportunity to clean up any
534 * resources if needed.
536 * \param device_handle - \c [in] Context associated with file
537 * descriptor for AMD GPU device
538 * received previously as the
539 * result e.g. of drmOpen() call.
541 * \return 0 on success\n
542 * >0 - AMD specific error code\n
543 * <0 - Negative POSIX Error code
545 * \sa amdgpu_device_initialize()
548 int amdgpu_device_deinitialize(amdgpu_device_handle device_handle);
557 * Allocate memory to be used by UMD for GPU related operations
559 * \param dev - \c [in] Device handle.
560 * See #amdgpu_device_initialize()
561 * \param alloc_buffer - \c [in] Pointer to the structure describing an
563 * \param info - \c [out] Pointer to structure which return
564 * information about allocated memory
566 * \return 0 on success\n
567 * >0 - AMD specific error code\n
568 * <0 - Negative POSIX Error code
570 * \sa amdgpu_bo_free()
572 int amdgpu_bo_alloc(amdgpu_device_handle dev,
573 struct amdgpu_bo_alloc_request *alloc_buffer,
574 struct amdgpu_bo_alloc_result *info);
577 * Associate opaque data with buffer to be queried by another UMD
579 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
580 * \param buf_handle - \c [in] Buffer handle
581 * \param info - \c [in] Metadata to associated with buffer
583 * \return 0 on success\n
584 * >0 - AMD specific error code\n
585 * <0 - Negative POSIX Error code
587 int amdgpu_bo_set_metadata(amdgpu_bo_handle buf_handle,
588 struct amdgpu_bo_metadata *info);
591 * Query buffer information including metadata previusly associated with
594 * \param dev - \c [in] Device handle.
595 * See #amdgpu_device_initialize()
596 * \param buf_handle - \c [in] Buffer handle
597 * \param info - \c [out] Structure describing buffer
599 * \return 0 on success\n
600 * >0 - AMD specific error code\n
601 * <0 - Negative POSIX Error code
603 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc()
605 int amdgpu_bo_query_info(amdgpu_bo_handle buf_handle,
606 struct amdgpu_bo_info *info);
609 * Allow others to get access to buffer
611 * \param dev - \c [in] Device handle.
612 * See #amdgpu_device_initialize()
613 * \param buf_handle - \c [in] Buffer handle
614 * \param type - \c [in] Type of handle requested
615 * \param shared_handle - \c [out] Special "shared" handle
617 * \return 0 on success\n
618 * >0 - AMD specific error code\n
619 * <0 - Negative POSIX Error code
621 * \sa amdgpu_bo_import()
624 int amdgpu_bo_export(amdgpu_bo_handle buf_handle,
625 enum amdgpu_bo_handle_type type,
626 uint32_t *shared_handle);
629 * Request access to "shared" buffer
631 * \param dev - \c [in] Device handle.
632 * See #amdgpu_device_initialize()
633 * \param type - \c [in] Type of handle requested
634 * \param shared_handle - \c [in] Shared handle received as result "import"
636 * \param output - \c [out] Pointer to structure with information
637 * about imported buffer
639 * \return 0 on success\n
640 * >0 - AMD specific error code\n
641 * <0 - Negative POSIX Error code
643 * \note Buffer must be "imported" only using new "fd" (different from
644 * one used by "exporter").
646 * \sa amdgpu_bo_export()
649 int amdgpu_bo_import(amdgpu_device_handle dev,
650 enum amdgpu_bo_handle_type type,
651 uint32_t shared_handle,
652 struct amdgpu_bo_import_result *output);
655 * Free previosuly allocated memory
657 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
658 * \param buf_handle - \c [in] Buffer handle to free
660 * \return 0 on success\n
661 * >0 - AMD specific error code\n
662 * <0 - Negative POSIX Error code
664 * \note In the case of memory shared between different applications all
665 * resources will be “physically” freed only all such applications
667 * \note If is UMD responsibility to ‘free’ buffer only when there is no
670 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc()
673 int amdgpu_bo_free(amdgpu_bo_handle buf_handle);
676 * Request CPU access to GPU accessable memory
678 * \param buf_handle - \c [in] Buffer handle
679 * \param cpu - \c [out] CPU address to be used for access
681 * \return 0 on success\n
682 * >0 - AMD specific error code\n
683 * <0 - Negative POSIX Error code
685 * \sa amdgpu_bo_cpu_unmap()
688 int amdgpu_bo_cpu_map(amdgpu_bo_handle buf_handle, void **cpu);
691 * Release CPU access to GPU memory
693 * \param buf_handle - \c [in] Buffer handle
695 * \return 0 on success\n
696 * >0 - AMD specific error code\n
697 * <0 - Negative POSIX Error code
699 * \sa amdgpu_bo_cpu_map()
702 int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle);
706 * Wait until a buffer is not used by the device.
708 * \param dev - \c [in] Device handle. See #amdgpu_lib_initialize()
709 * \param buf_handle - \c [in] Buffer handle.
710 * \param timeout_ns - Timeout in nanoseconds.
711 * \param buffer_busy - 0 if buffer is idle, all GPU access was completed
712 * and no GPU access is scheduled.
713 * 1 GPU access is in fly or scheduled
715 * \return 0 - on success
716 * <0 - AMD specific error code
718 int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle,
723 * Creates a BO list handle for command submission.
725 * \param dev - \c [in] Device handle.
726 * See #amdgpu_device_initialize()
727 * \param number_of_resources - \c [in] Number of BOs in the list
728 * \param resources - \c [in] List of BO handles
729 * \param resource_prios - \c [in] Optional priority for each handle
730 * \param result - \c [out] Created BO list handle
732 * \return 0 on success\n
733 * >0 - AMD specific error code\n
734 * <0 - Negative POSIX Error code
736 * \sa amdgpu_bo_list_destroy()
738 int amdgpu_bo_list_create(amdgpu_device_handle dev,
739 uint32_t number_of_resources,
740 amdgpu_bo_handle *resources,
741 uint8_t *resource_prios,
742 amdgpu_bo_list_handle *result);
745 * Destroys a BO list handle.
747 * \param handle - \c [in] BO list handle.
749 * \return 0 on success\n
750 * >0 - AMD specific error code\n
751 * <0 - Negative POSIX Error code
753 * \sa amdgpu_bo_list_create()
755 int amdgpu_bo_list_destroy(amdgpu_bo_list_handle handle);
758 * Update resources for existing BO list
760 * \param handle - \c [in] BO list handle
761 * \param number_of_resources - \c [in] Number of BOs in the list
762 * \param resources - \c [in] List of BO handles
763 * \param resource_prios - \c [in] Optional priority for each handle
765 * \return 0 on success\n
766 * >0 - AMD specific error code\n
767 * <0 - Negative POSIX Error code
769 * \sa amdgpu_bo_list_update()
771 int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
772 uint32_t number_of_resources,
773 amdgpu_bo_handle *resources,
774 uint8_t *resource_prios);
777 * Special GPU Resources
784 * Query information about GDS
786 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
787 * \param gds_info - \c [out] Pointer to structure to get GDS information
789 * \return 0 on success\n
790 * >0 - AMD specific error code\n
791 * <0 - Negative POSIX Error code
794 int amdgpu_query_gds_info(amdgpu_device_handle dev,
795 struct amdgpu_gds_resource_info *gds_info);
799 * GPU Execution context
804 * Create GPU execution Context
806 * For the purpose of GPU Scheduler and GPU Robustness extensions it is
807 * necessary to have information/identify rendering/compute contexts.
808 * It also may be needed to associate some specific requirements with such
809 * contexts. Kernel driver will guarantee that submission from the same
810 * context will always be executed in order (first come, first serve).
813 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
814 * \param context - \c [out] GPU Context handle
816 * \return 0 on success\n
817 * >0 - AMD specific error code\n
818 * <0 - Negative POSIX Error code
820 * \sa amdgpu_cs_ctx_free()
823 int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
824 amdgpu_context_handle *context);
828 * Destroy GPU execution context when not needed any more
830 * \param context - \c [in] GPU Context handle
832 * \return 0 on success\n
833 * >0 - AMD specific error code\n
834 * <0 - Negative POSIX Error code
836 * \sa amdgpu_cs_ctx_create()
839 int amdgpu_cs_ctx_free(amdgpu_context_handle context);
842 * Query reset state for the specific GPU Context
844 * \param context - \c [in] GPU Context handle
845 * \param state - \c [out] One of AMDGPU_CTX_*_RESET
846 * \param hangs - \c [out] Number of hangs caused by the context.
848 * \return 0 on success\n
849 * >0 - AMD specific error code\n
850 * <0 - Negative POSIX Error code
852 * \sa amdgpu_cs_ctx_create()
855 int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
856 uint32_t *state, uint32_t *hangs);
860 * Command Buffers Management
865 * Send request to submit command buffers to hardware.
867 * Kernel driver could use GPU Scheduler to make decision when physically
868 * sent this request to the hardware. Accordingly this request could be put
869 * in queue and sent for execution later. The only guarantee is that request
870 * from the same GPU context to the same ip:ip_instance:ring will be executed in
874 * \param dev - \c [in] Device handle.
875 * See #amdgpu_device_initialize()
876 * \param context - \c [in] GPU Context
877 * \param flags - \c [in] Global submission flags
878 * \param ibs_request - \c [in] Pointer to submission requests.
879 * We could submit to the several
880 * engines/rings simulteniously as
882 * \param number_of_requests - \c [in] Number of submission requests
883 * \param fences - \c [out] Pointer to array of data to get
884 * fences to identify submission
885 * requests. Timestamps are valid
886 * in this GPU context and could be used
887 * to identify/detect completion of
890 * \return 0 on success\n
891 * >0 - AMD specific error code\n
892 * <0 - Negative POSIX Error code
894 * \note It is required to pass correct resource list with buffer handles
895 * which will be accessible by command buffers from submission
896 * This will allow kernel driver to correctly implement "paging".
897 * Failure to do so will have unpredictable results.
899 * \sa amdgpu_command_buffer_alloc(), amdgpu_command_buffer_free(),
900 * amdgpu_cs_query_fence_status()
903 int amdgpu_cs_submit(amdgpu_context_handle context,
905 struct amdgpu_cs_request *ibs_request,
906 uint32_t number_of_requests,
910 * Query status of Command Buffer Submission
912 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
913 * \param fence - \c [in] Structure describing fence to query
914 * \param expired - \c [out] If fence expired or not.\n
915 * 0 – if fence is not expired\n
918 * \return 0 on success\n
919 * >0 - AMD specific error code\n
920 * <0 - Negative POSIX Error code
922 * \note If UMD wants only to check operation status and returned immediately
923 * then timeout value as 0 must be passed. In this case success will be
924 * returned in the case if submission was completed or timeout error
927 * \sa amdgpu_cs_submit()
929 int amdgpu_cs_query_fence_status(struct amdgpu_cs_query_fence *fence,
940 * Query allocation size alignments
942 * UMD should query information about GPU VM MC size alignments requirements
943 * to be able correctly choose required allocation size and implement
944 * internal optimization if needed.
946 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
947 * \param info - \c [out] Pointer to structure to get size alignment
950 * \return 0 on success\n
951 * >0 - AMD specific error code\n
952 * <0 - Negative POSIX Error code
955 int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
956 struct amdgpu_buffer_size_alignments
962 * Query firmware versions
964 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
965 * \param fw_type - \c [in] AMDGPU_INFO_FW_*
966 * \param ip_instance - \c [in] Index of the IP block of the same type.
967 * \param index - \c [in] Index of the engine. (for SDMA and MEC)
968 * \param version - \c [out] Pointer to to the "version" return value
969 * \param feature - \c [out] Pointer to to the "feature" return value
971 * \return 0 on success\n
972 * >0 - AMD specific error code\n
973 * <0 - Negative POSIX Error code
976 int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
977 unsigned ip_instance, unsigned index,
978 uint32_t *version, uint32_t *feature);
983 * Query the number of HW IP instances of a certain type.
985 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
986 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
987 * \param count - \c [out] Pointer to structure to get information
989 * \return 0 on success\n
990 * >0 - AMD specific error code\n
991 * <0 - Negative POSIX Error code
993 int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type,
999 * Query engine information
1001 * This query allows UMD to query information different engines and their
1004 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1005 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
1006 * \param ip_instance - \c [in] Index of the IP block of the same type.
1007 * \param info - \c [out] Pointer to structure to get information
1009 * \return 0 on success\n
1010 * >0 - AMD specific error code\n
1011 * <0 - Negative POSIX Error code
1013 int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
1014 unsigned ip_instance,
1015 struct drm_amdgpu_info_hw_ip *info);
1021 * Query heap information
1023 * This query allows UMD to query potentially available memory resources and
1024 * adjust their logic if necessary.
1026 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1027 * \param heap - \c [in] Heap type
1028 * \param info - \c [in] Pointer to structure to get needed information
1030 * \return 0 on success\n
1031 * >0 - AMD specific error code\n
1032 * <0 - Negative POSIX Error code
1035 int amdgpu_query_heap_info(amdgpu_device_handle dev,
1038 struct amdgpu_heap_info *info);
1043 * Get the CRTC ID from the mode object ID
1045 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1046 * \param id - \c [in] Mode object ID
1047 * \param result - \c [in] Pointer to the CRTC ID
1049 * \return 0 on success\n
1050 * >0 - AMD specific error code\n
1051 * <0 - Negative POSIX Error code
1054 int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
1060 * Query GPU H/w Info
1062 * Query hardware specific information
1064 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1065 * \param heap - \c [in] Heap type
1066 * \param info - \c [in] Pointer to structure to get needed information
1068 * \return 0 on success\n
1069 * >0 - AMD specific error code\n
1070 * <0 - Negative POSIX Error code
1073 int amdgpu_query_gpu_info(amdgpu_device_handle dev,
1074 struct amdgpu_gpu_info *info);
1079 * Query hardware or driver information.
1081 * The return size is query-specific and depends on the "info_id" parameter.
1082 * No more than "size" bytes is returned.
1084 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1085 * \param info_id - \c [in] AMDGPU_INFO_*
1086 * \param size - \c [in] Size of the returned value.
1087 * \param value - \c [out] Pointer to the return value.
1089 * \return 0 on success\n
1090 * >0 - AMD specific error code\n
1091 * <0 - Negative POSIX error code
1094 int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
1095 unsigned size, void *value);
1100 * Read a set of consecutive memory-mapped registers.
1101 * Not all registers are allowed to be read by userspace.
1103 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize(
1104 * \param dword_offset - \c [in] Register offset in dwords
1105 * \param count - \c [in] The number of registers to read starting
1107 * \param instance - \c [in] GRBM_GFX_INDEX selector. It may have other
1108 * uses. Set it to 0xffffffff if unsure.
1109 * \param flags - \c [in] Flags with additional information.
1110 * \param values - \c [out] The pointer to return values.
1112 * \return 0 on success\n
1113 * >0 - AMD specific error code\n
1114 * <0 - Negative POSIX error code
1117 int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
1118 unsigned count, uint32_t instance, uint32_t flags,
1124 * Request GPU access to user allocated memory e.g. via "malloc"
1126 * \param dev - [in] Device handle. See #amdgpu_device_initialize()
1127 * \param cpu - [in] CPU address of user allocated memory which we
1128 * want to map to GPU address space (make GPU accessible)
1129 * (This address must be correctly aligned).
1130 * \param size - [in] Size of allocation (must be correctly aligned)
1131 * \param amdgpu_bo_alloc_result - [out] Handle of allocation to be passed as resource
1132 * on submission and be used in other operations.(e.g. for VA submission)
1133 * ( Temporally defined amdgpu_bo_alloc_result as parameter for return mc address. )
1136 * \return 0 on success
1137 * >0 - AMD specific error code
1138 * <0 - Negative POSIX Error code
1142 * This call doesn't guarantee that such memory will be persistently
1143 * "locked" / make non-pageable. The purpose of this call is to provide
1144 * opportunity for GPU get access to this resource during submission.
1146 * The maximum amount of memory which could be mapped in this call depends
1147 * if overcommit is disabled or not. If overcommit is disabled than the max.
1148 * amount of memory to be pinned will be limited by left "free" size in total
1149 * amount of memory which could be locked simultaneously ("GART" size).
1151 * Supported (theoretical) max. size of mapping is restricted only by
1154 * It is responsibility of caller to correctly specify access rights
1157 int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
1160 struct amdgpu_bo_alloc_result *info);
1163 #endif /* #ifdef _AMDGPU_H_ */