2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 * Declare public libdrm_amdgpu API
29 * This file define API exposed by libdrm_amdgpu library.
30 * User wanted to use libdrm_amdgpu functionality must include
44 struct drm_amdgpu_info_hw_ip;
45 struct drm_amdgpu_bo_list_entry;
47 /*--------------------------------------------------------------------------*/
48 /* --------------------------- Defines ------------------------------------ */
49 /*--------------------------------------------------------------------------*/
52 * Define max. number of Command Buffers (IB) which could be sent to the single
53 * hardware IP to accommodate CE/DE requirements
55 * \sa amdgpu_cs_ib_info
57 #define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4
60 * Special timeout value meaning that the timeout is infinite.
62 #define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull
65 * Used in amdgpu_cs_query_fence_status(), meaning that the given timeout
68 #define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0)
70 /*--------------------------------------------------------------------------*/
71 /* ----------------------------- Enums ------------------------------------ */
72 /*--------------------------------------------------------------------------*/
75 * Enum describing possible handle types
77 * \sa amdgpu_bo_import, amdgpu_bo_export
80 enum amdgpu_bo_handle_type {
81 /** GEM flink name (needs DRM authentication, used by DRI2) */
82 amdgpu_bo_handle_type_gem_flink_name = 0,
84 /** KMS handle which is used by all driver ioctls */
85 amdgpu_bo_handle_type_kms = 1,
87 /** DMA-buf fd handle */
88 amdgpu_bo_handle_type_dma_buf_fd = 2,
90 /** Deprecated in favour of and same behaviour as
91 * amdgpu_bo_handle_type_kms, use that instead of this
93 amdgpu_bo_handle_type_kms_noimport = 3,
96 /** Define known types of GPU VM VA ranges */
97 enum amdgpu_gpu_va_range
99 /** Allocate from "normal"/general range */
100 amdgpu_gpu_va_range_general = 0
103 enum amdgpu_sw_info {
104 amdgpu_sw_info_address32_hi = 0,
107 /*--------------------------------------------------------------------------*/
108 /* -------------------------- Datatypes ----------------------------------- */
109 /*--------------------------------------------------------------------------*/
112 * Define opaque pointer to context associated with fd.
113 * This context will be returned as the result of
114 * "initialize" function and should be pass as the first
115 * parameter to any API call
117 typedef struct amdgpu_device *amdgpu_device_handle;
120 * Define GPU Context type as pointer to opaque structure
121 * Example of GPU Context is the "rendering" context associated
122 * with OpenGL context (glCreateContext)
124 typedef struct amdgpu_context *amdgpu_context_handle;
127 * Define handle for amdgpu resources: buffer, GDS, etc.
129 typedef struct amdgpu_bo *amdgpu_bo_handle;
132 * Define handle for list of BOs
134 typedef struct amdgpu_bo_list *amdgpu_bo_list_handle;
137 * Define handle to be used to work with VA allocated ranges
139 typedef struct amdgpu_va *amdgpu_va_handle;
142 * Define handle for semaphore
144 typedef struct amdgpu_semaphore *amdgpu_semaphore_handle;
146 /*--------------------------------------------------------------------------*/
147 /* -------------------------- Structures ---------------------------------- */
148 /*--------------------------------------------------------------------------*/
151 * Structure describing memory allocation request
153 * \sa amdgpu_bo_alloc()
156 struct amdgpu_bo_alloc_request {
157 /** Allocation request. It must be aligned correctly. */
161 * It may be required to have some specific alignment requirements
162 * for physical back-up storage (e.g. for displayable surface).
163 * If 0 there is no special alignment requirement
165 uint64_t phys_alignment;
168 * UMD should specify where to allocate memory and how it
169 * will be accessed by the CPU.
171 uint32_t preferred_heap;
173 /** Additional flags passed on allocation */
178 * Special UMD specific information associated with buffer.
180 * It may be need to pass some buffer charactersitic as part
181 * of buffer sharing. Such information are defined UMD and
182 * opaque for libdrm_amdgpu as well for kernel driver.
184 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info,
185 * amdgpu_bo_import(), amdgpu_bo_export
188 struct amdgpu_bo_metadata {
189 /** Special flag associated with surface */
193 * ASIC-specific tiling information (also used by DCE).
194 * The encoding is defined by the AMDGPU_TILING_* definitions.
196 uint64_t tiling_info;
198 /** Size of metadata associated with the buffer, in bytes. */
199 uint32_t size_metadata;
201 /** UMD specific metadata. Opaque for kernel */
202 uint32_t umd_metadata[64];
206 * Structure describing allocated buffer. Client may need
207 * to query such information as part of 'sharing' buffers mechanism
209 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info(),
210 * amdgpu_bo_import(), amdgpu_bo_export()
212 struct amdgpu_bo_info {
213 /** Allocated memory size */
217 * It may be required to have some specific alignment requirements
218 * for physical back-up storage.
220 uint64_t phys_alignment;
222 /** Heap where to allocate memory. */
223 uint32_t preferred_heap;
225 /** Additional allocation flags. */
226 uint64_t alloc_flags;
228 /** Metadata associated with buffer if any. */
229 struct amdgpu_bo_metadata metadata;
233 * Structure with information about "imported" buffer
235 * \sa amdgpu_bo_import()
238 struct amdgpu_bo_import_result {
239 /** Handle of memory/buffer to use */
240 amdgpu_bo_handle buf_handle;
248 * Structure to describe GDS partitioning information.
249 * \note OA and GWS resources are asscoiated with GDS partition
251 * \sa amdgpu_gpu_resource_query_gds_info
254 struct amdgpu_gds_resource_info {
255 uint32_t gds_gfx_partition_size;
256 uint32_t compute_partition_size;
257 uint32_t gds_total_size;
258 uint32_t gws_per_gfx_partition;
259 uint32_t gws_per_compute_partition;
260 uint32_t oa_per_gfx_partition;
261 uint32_t oa_per_compute_partition;
265 * Structure describing CS fence
267 * \sa amdgpu_cs_query_fence_status(), amdgpu_cs_request, amdgpu_cs_submit()
270 struct amdgpu_cs_fence {
272 /** In which context IB was sent to execution */
273 amdgpu_context_handle context;
275 /** To which HW IP type the fence belongs */
278 /** IP instance index if there are several IPs of the same type. */
279 uint32_t ip_instance;
281 /** Ring index of the HW IP */
284 /** Specify fence for which we need to check submission status.*/
289 * Structure describing IB
291 * \sa amdgpu_cs_request, amdgpu_cs_submit()
294 struct amdgpu_cs_ib_info {
298 /** Virtual MC address of the command buffer */
299 uint64_t ib_mc_address;
302 * Size of Command Buffer to be submitted.
303 * - The size is in units of dwords (4 bytes).
310 * Structure describing fence information
312 * \sa amdgpu_cs_request, amdgpu_cs_query_fence,
313 * amdgpu_cs_submit(), amdgpu_cs_query_fence_status()
315 struct amdgpu_cs_fence_info {
316 /** buffer object for the fence */
317 amdgpu_bo_handle handle;
319 /** fence offset in the unit of sizeof(uint64_t) */
324 * Structure describing submission request
326 * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx
328 * \sa amdgpu_cs_submit()
330 struct amdgpu_cs_request {
331 /** Specify flags with additional information */
334 /** Specify HW IP block type to which to send the IB. */
337 /** IP instance index if there are several IPs of the same type. */
338 unsigned ip_instance;
341 * Specify ring index of the IP. We could have several rings
342 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1.
347 * List handle with resources used by this request.
349 amdgpu_bo_list_handle resources;
352 * Number of dependencies this Command submission needs to
353 * wait for before starting execution.
355 uint32_t number_of_dependencies;
358 * Array of dependencies which need to be met before
359 * execution can start.
361 struct amdgpu_cs_fence *dependencies;
363 /** Number of IBs to submit in the field ibs. */
364 uint32_t number_of_ibs;
367 * IBs to submit. Those IBs will be submit together as single entity
369 struct amdgpu_cs_ib_info *ibs;
372 * The returned sequence number for the command submission
377 * The fence information
379 struct amdgpu_cs_fence_info fence_info;
383 * Structure which provide information about GPU VM MC Address space
384 * alignments requirements
386 * \sa amdgpu_query_buffer_size_alignment
388 struct amdgpu_buffer_size_alignments {
389 /** Size alignment requirement for allocation in
394 * Size alignment requirement for allocation in remote memory
396 uint64_t size_remote;
400 * Structure which provide information about heap
402 * \sa amdgpu_query_heap_info()
405 struct amdgpu_heap_info {
406 /** Theoretical max. available memory in the given heap */
410 * Number of bytes allocated in the heap. This includes all processes
411 * and private allocations in the kernel. It changes when new buffers
412 * are allocated, freed, and moved. It cannot be larger than
418 * Theoretical possible max. size of buffer which
419 * could be allocated in the given heap
421 uint64_t max_allocation;
425 * Describe GPU h/w info needed for UMD correct initialization
427 * \sa amdgpu_query_gpu_info()
429 struct amdgpu_gpu_info {
434 /** Chip external revision */
435 uint32_t chip_external_rev;
440 /** max engine clock*/
441 uint64_t max_engine_clk;
442 /** max memory clock */
443 uint64_t max_memory_clk;
444 /** number of shader engines */
445 uint32_t num_shader_engines;
446 /** number of shader arrays per engine */
447 uint32_t num_shader_arrays_per_engine;
448 /** Number of available good shader pipes */
449 uint32_t avail_quad_shader_pipes;
450 /** Max. number of shader pipes.(including good and bad pipes */
451 uint32_t max_quad_shader_pipes;
452 /** Number of parameter cache entries per shader quad pipe */
453 uint32_t cache_entries_per_quad_pipe;
454 /** Number of available graphics context */
455 uint32_t num_hw_gfx_contexts;
456 /** Number of render backend pipes */
458 /** Enabled render backend pipe mask */
459 uint32_t enabled_rb_pipes_mask;
460 /** Frequency of GPU Counter */
461 uint32_t gpu_counter_freq;
462 /** CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE */
463 uint32_t backend_disable[4];
464 /** Value of MC_ARB_RAMCFG register*/
465 uint32_t mc_arb_ramcfg;
466 /** Value of GB_ADDR_CONFIG */
467 uint32_t gb_addr_cfg;
468 /** Values of the GB_TILE_MODE0..31 registers */
469 uint32_t gb_tile_mode[32];
470 /** Values of GB_MACROTILE_MODE0..15 registers */
471 uint32_t gb_macro_tile_mode[16];
472 /** Value of PA_SC_RASTER_CONFIG register per SE */
473 uint32_t pa_sc_raster_cfg[4];
474 /** Value of PA_SC_RASTER_CONFIG_1 register per SE */
475 uint32_t pa_sc_raster_cfg1[4];
477 uint32_t cu_active_number;
479 uint32_t cu_bitmap[4][4];
480 /* video memory type info*/
482 /* video memory bit width*/
483 uint32_t vram_bit_width;
484 /** constant engine ram size*/
485 uint32_t ce_ram_size;
486 /* vce harvesting instance */
487 uint32_t vce_harvest_config;
488 /* PCI revision ID */
493 /*--------------------------------------------------------------------------*/
494 /*------------------------- Functions --------------------------------------*/
495 /*--------------------------------------------------------------------------*/
498 * Initialization / Cleanup
504 * \param fd - \c [in] File descriptor for AMD GPU device
505 * received previously as the result of
506 * e.g. drmOpen() call.
507 * For legacy fd type, the DRI2/DRI3
508 * authentication should be done before
509 * calling this function.
510 * \param major_version - \c [out] Major version of library. It is assumed
511 * that adding new functionality will cause
512 * increase in major version
513 * \param minor_version - \c [out] Minor version of library
514 * \param device_handle - \c [out] Pointer to opaque context which should
515 * be passed as the first parameter on each
519 * \return 0 on success\n
520 * <0 - Negative POSIX Error code
523 * \sa amdgpu_device_deinitialize()
525 int amdgpu_device_initialize(int fd,
526 uint32_t *major_version,
527 uint32_t *minor_version,
528 amdgpu_device_handle *device_handle);
532 * When access to such library does not needed any more the special
533 * function must be call giving opportunity to clean up any
534 * resources if needed.
536 * \param device_handle - \c [in] Context associated with file
537 * descriptor for AMD GPU device
538 * received previously as the
539 * result e.g. of drmOpen() call.
541 * \return 0 on success\n
542 * <0 - Negative POSIX Error code
544 * \sa amdgpu_device_initialize()
547 int amdgpu_device_deinitialize(amdgpu_device_handle device_handle);
555 * Allocate memory to be used by UMD for GPU related operations
557 * \param dev - \c [in] Device handle.
558 * See #amdgpu_device_initialize()
559 * \param alloc_buffer - \c [in] Pointer to the structure describing an
561 * \param buf_handle - \c [out] Allocated buffer handle
563 * \return 0 on success\n
564 * <0 - Negative POSIX Error code
566 * \sa amdgpu_bo_free()
568 int amdgpu_bo_alloc(amdgpu_device_handle dev,
569 struct amdgpu_bo_alloc_request *alloc_buffer,
570 amdgpu_bo_handle *buf_handle);
573 * Associate opaque data with buffer to be queried by another UMD
575 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
576 * \param buf_handle - \c [in] Buffer handle
577 * \param info - \c [in] Metadata to associated with buffer
579 * \return 0 on success\n
580 * <0 - Negative POSIX Error code
582 int amdgpu_bo_set_metadata(amdgpu_bo_handle buf_handle,
583 struct amdgpu_bo_metadata *info);
586 * Query buffer information including metadata previusly associated with
589 * \param dev - \c [in] Device handle.
590 * See #amdgpu_device_initialize()
591 * \param buf_handle - \c [in] Buffer handle
592 * \param info - \c [out] Structure describing buffer
594 * \return 0 on success\n
595 * <0 - Negative POSIX Error code
597 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc()
599 int amdgpu_bo_query_info(amdgpu_bo_handle buf_handle,
600 struct amdgpu_bo_info *info);
603 * Allow others to get access to buffer
605 * \param dev - \c [in] Device handle.
606 * See #amdgpu_device_initialize()
607 * \param buf_handle - \c [in] Buffer handle
608 * \param type - \c [in] Type of handle requested
609 * \param shared_handle - \c [out] Special "shared" handle
611 * \return 0 on success\n
612 * <0 - Negative POSIX Error code
614 * \sa amdgpu_bo_import()
617 int amdgpu_bo_export(amdgpu_bo_handle buf_handle,
618 enum amdgpu_bo_handle_type type,
619 uint32_t *shared_handle);
622 * Request access to "shared" buffer
624 * \param dev - \c [in] Device handle.
625 * See #amdgpu_device_initialize()
626 * \param type - \c [in] Type of handle requested
627 * \param shared_handle - \c [in] Shared handle received as result "import"
629 * \param output - \c [out] Pointer to structure with information
630 * about imported buffer
632 * \return 0 on success\n
633 * <0 - Negative POSIX Error code
635 * \note Buffer must be "imported" only using new "fd" (different from
636 * one used by "exporter").
638 * \sa amdgpu_bo_export()
641 int amdgpu_bo_import(amdgpu_device_handle dev,
642 enum amdgpu_bo_handle_type type,
643 uint32_t shared_handle,
644 struct amdgpu_bo_import_result *output);
647 * Request GPU access to user allocated memory e.g. via "malloc"
649 * \param dev - [in] Device handle. See #amdgpu_device_initialize()
650 * \param cpu - [in] CPU address of user allocated memory which we
651 * want to map to GPU address space (make GPU accessible)
652 * (This address must be correctly aligned).
653 * \param size - [in] Size of allocation (must be correctly aligned)
654 * \param buf_handle - [out] Buffer handle for the userptr memory
655 * resource on submission and be used in other operations.
658 * \return 0 on success\n
659 * <0 - Negative POSIX Error code
662 * This call doesn't guarantee that such memory will be persistently
663 * "locked" / make non-pageable. The purpose of this call is to provide
664 * opportunity for GPU get access to this resource during submission.
666 * The maximum amount of memory which could be mapped in this call depends
667 * if overcommit is disabled or not. If overcommit is disabled than the max.
668 * amount of memory to be pinned will be limited by left "free" size in total
669 * amount of memory which could be locked simultaneously ("GART" size).
671 * Supported (theoretical) max. size of mapping is restricted only by
674 * It is responsibility of caller to correctly specify access rights
677 int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
678 void *cpu, uint64_t size,
679 amdgpu_bo_handle *buf_handle);
682 * Validate if the user memory comes from BO
684 * \param dev - [in] Device handle. See #amdgpu_device_initialize()
685 * \param cpu - [in] CPU address of user allocated memory which we
686 * want to map to GPU address space (make GPU accessible)
687 * (This address must be correctly aligned).
688 * \param size - [in] Size of allocation (must be correctly aligned)
689 * \param buf_handle - [out] Buffer handle for the userptr memory
690 * if the user memory is not from BO, the buf_handle will be NULL.
691 * \param offset_in_bo - [out] offset in this BO for this user memory
694 * \return 0 on success\n
695 * <0 - Negative POSIX Error code
698 int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
701 amdgpu_bo_handle *buf_handle,
702 uint64_t *offset_in_bo);
705 * Free previously allocated memory
707 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
708 * \param buf_handle - \c [in] Buffer handle to free
710 * \return 0 on success\n
711 * <0 - Negative POSIX Error code
713 * \note In the case of memory shared between different applications all
714 * resources will be “physically” freed only all such applications
716 * \note If is UMD responsibility to ‘free’ buffer only when there is no
719 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc()
722 int amdgpu_bo_free(amdgpu_bo_handle buf_handle);
725 * Increase the reference count of a buffer object
727 * \param bo - \c [in] Buffer object handle to increase the reference count
729 * \sa amdgpu_bo_alloc(), amdgpu_bo_free()
732 void amdgpu_bo_inc_ref(amdgpu_bo_handle bo);
735 * Request CPU access to GPU accessible memory
737 * \param buf_handle - \c [in] Buffer handle
738 * \param cpu - \c [out] CPU address to be used for access
740 * \return 0 on success\n
741 * <0 - Negative POSIX Error code
743 * \sa amdgpu_bo_cpu_unmap()
746 int amdgpu_bo_cpu_map(amdgpu_bo_handle buf_handle, void **cpu);
749 * Release CPU access to GPU memory
751 * \param buf_handle - \c [in] Buffer handle
753 * \return 0 on success\n
754 * <0 - Negative POSIX Error code
756 * \sa amdgpu_bo_cpu_map()
759 int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle);
762 * Wait until a buffer is not used by the device.
764 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
765 * \param buf_handle - \c [in] Buffer handle.
766 * \param timeout_ns - Timeout in nanoseconds.
767 * \param buffer_busy - 0 if buffer is idle, all GPU access was completed
768 * and no GPU access is scheduled.
769 * 1 GPU access is in fly or scheduled
771 * \return 0 - on success
772 * <0 - Negative POSIX Error code
774 int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle,
779 * Creates a BO list handle for command submission.
781 * \param dev - \c [in] Device handle.
782 * See #amdgpu_device_initialize()
783 * \param number_of_buffers - \c [in] Number of BOs in the list
784 * \param buffers - \c [in] List of BO handles
785 * \param result - \c [out] Created BO list handle
787 * \return 0 on success\n
788 * <0 - Negative POSIX Error code
790 * \sa amdgpu_bo_list_destroy_raw(), amdgpu_cs_submit_raw2()
792 int amdgpu_bo_list_create_raw(amdgpu_device_handle dev,
793 uint32_t number_of_buffers,
794 struct drm_amdgpu_bo_list_entry *buffers,
798 * Destroys a BO list handle.
800 * \param bo_list - \c [in] BO list handle.
802 * \return 0 on success\n
803 * <0 - Negative POSIX Error code
805 * \sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2()
807 int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, uint32_t bo_list);
810 * Creates a BO list handle for command submission.
812 * \param dev - \c [in] Device handle.
813 * See #amdgpu_device_initialize()
814 * \param number_of_resources - \c [in] Number of BOs in the list
815 * \param resources - \c [in] List of BO handles
816 * \param resource_prios - \c [in] Optional priority for each handle
817 * \param result - \c [out] Created BO list handle
819 * \return 0 on success\n
820 * <0 - Negative POSIX Error code
822 * \sa amdgpu_bo_list_destroy()
824 int amdgpu_bo_list_create(amdgpu_device_handle dev,
825 uint32_t number_of_resources,
826 amdgpu_bo_handle *resources,
827 uint8_t *resource_prios,
828 amdgpu_bo_list_handle *result);
831 * Destroys a BO list handle.
833 * \param handle - \c [in] BO list handle.
835 * \return 0 on success\n
836 * <0 - Negative POSIX Error code
838 * \sa amdgpu_bo_list_create()
840 int amdgpu_bo_list_destroy(amdgpu_bo_list_handle handle);
843 * Update resources for existing BO list
845 * \param handle - \c [in] BO list handle
846 * \param number_of_resources - \c [in] Number of BOs in the list
847 * \param resources - \c [in] List of BO handles
848 * \param resource_prios - \c [in] Optional priority for each handle
850 * \return 0 on success\n
851 * <0 - Negative POSIX Error code
853 * \sa amdgpu_bo_list_update()
855 int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
856 uint32_t number_of_resources,
857 amdgpu_bo_handle *resources,
858 uint8_t *resource_prios);
861 * GPU Execution context
866 * Create GPU execution Context
868 * For the purpose of GPU Scheduler and GPU Robustness extensions it is
869 * necessary to have information/identify rendering/compute contexts.
870 * It also may be needed to associate some specific requirements with such
871 * contexts. Kernel driver will guarantee that submission from the same
872 * context will always be executed in order (first come, first serve).
875 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
876 * \param priority - \c [in] Context creation flags. See AMDGPU_CTX_PRIORITY_*
877 * \param context - \c [out] GPU Context handle
879 * \return 0 on success\n
880 * <0 - Negative POSIX Error code
882 * \sa amdgpu_cs_ctx_free()
885 int amdgpu_cs_ctx_create2(amdgpu_device_handle dev,
887 amdgpu_context_handle *context);
889 * Create GPU execution Context
891 * Refer to amdgpu_cs_ctx_create2 for full documentation. This call
892 * is missing the priority parameter.
894 * \sa amdgpu_cs_ctx_create2()
897 int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
898 amdgpu_context_handle *context);
902 * Destroy GPU execution context when not needed any more
904 * \param context - \c [in] GPU Context handle
906 * \return 0 on success\n
907 * <0 - Negative POSIX Error code
909 * \sa amdgpu_cs_ctx_create()
912 int amdgpu_cs_ctx_free(amdgpu_context_handle context);
915 * Override the submission priority for the given context using a master fd.
917 * \param dev - \c [in] device handle
918 * \param context - \c [in] context handle for context id
919 * \param master_fd - \c [in] The master fd to authorize the override.
920 * \param priority - \c [in] The priority to assign to the context.
922 * \return 0 on success or a a negative Posix error code on failure.
924 int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev,
925 amdgpu_context_handle context,
930 * Query reset state for the specific GPU Context
932 * \param context - \c [in] GPU Context handle
933 * \param state - \c [out] One of AMDGPU_CTX_*_RESET
934 * \param hangs - \c [out] Number of hangs caused by the context.
936 * \return 0 on success\n
937 * <0 - Negative POSIX Error code
939 * \sa amdgpu_cs_ctx_create()
942 int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
943 uint32_t *state, uint32_t *hangs);
946 * Query reset state for the specific GPU Context.
948 * \param context - \c [in] GPU Context handle
949 * \param flags - \c [out] A combination of AMDGPU_CTX_QUERY2_FLAGS_*
951 * \return 0 on success\n
952 * <0 - Negative POSIX Error code
954 * \sa amdgpu_cs_ctx_create()
957 int amdgpu_cs_query_reset_state2(amdgpu_context_handle context,
961 * Command Buffers Management
966 * Send request to submit command buffers to hardware.
968 * Kernel driver could use GPU Scheduler to make decision when physically
969 * sent this request to the hardware. Accordingly this request could be put
970 * in queue and sent for execution later. The only guarantee is that request
971 * from the same GPU context to the same ip:ip_instance:ring will be executed in
974 * The caller can specify the user fence buffer/location with the fence_info in the
975 * cs_request.The sequence number is returned via the 'seq_no' parameter
976 * in ibs_request structure.
979 * \param dev - \c [in] Device handle.
980 * See #amdgpu_device_initialize()
981 * \param context - \c [in] GPU Context
982 * \param flags - \c [in] Global submission flags
983 * \param ibs_request - \c [in/out] Pointer to submission requests.
984 * We could submit to the several
985 * engines/rings simulteniously as
987 * \param number_of_requests - \c [in] Number of submission requests
989 * \return 0 on success\n
990 * <0 - Negative POSIX Error code
992 * \note It is required to pass correct resource list with buffer handles
993 * which will be accessible by command buffers from submission
994 * This will allow kernel driver to correctly implement "paging".
995 * Failure to do so will have unpredictable results.
997 * \sa amdgpu_command_buffer_alloc(), amdgpu_command_buffer_free(),
998 * amdgpu_cs_query_fence_status()
1001 int amdgpu_cs_submit(amdgpu_context_handle context,
1003 struct amdgpu_cs_request *ibs_request,
1004 uint32_t number_of_requests);
1007 * Query status of Command Buffer Submission
1009 * \param fence - \c [in] Structure describing fence to query
1010 * \param timeout_ns - \c [in] Timeout value to wait
1011 * \param flags - \c [in] Flags for the query
1012 * \param expired - \c [out] If fence expired or not.\n
1013 * 0 – if fence is not expired\n
1016 * \return 0 on success\n
1017 * <0 - Negative POSIX Error code
1019 * \note If UMD wants only to check operation status and returned immediately
1020 * then timeout value as 0 must be passed. In this case success will be
1021 * returned in the case if submission was completed or timeout error
1024 * \sa amdgpu_cs_submit()
1026 int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
1027 uint64_t timeout_ns,
1032 * Wait for multiple fences
1034 * \param fences - \c [in] The fence array to wait
1035 * \param fence_count - \c [in] The fence count
1036 * \param wait_all - \c [in] If true, wait all fences to be signaled,
1037 * otherwise, wait at least one fence
1038 * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds
1039 * \param status - \c [out] '1' for signaled, '0' for timeout
1040 * \param first - \c [out] the index of the first signaled fence from @fences
1042 * \return 0 on success
1043 * <0 - Negative POSIX Error code
1045 * \note Currently it supports only one amdgpu_device. All fences come from
1046 * the same amdgpu_device with the same fd.
1048 int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences,
1049 uint32_t fence_count,
1051 uint64_t timeout_ns,
1052 uint32_t *status, uint32_t *first);
1060 * Query allocation size alignments
1062 * UMD should query information about GPU VM MC size alignments requirements
1063 * to be able correctly choose required allocation size and implement
1064 * internal optimization if needed.
1066 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1067 * \param info - \c [out] Pointer to structure to get size alignment
1070 * \return 0 on success\n
1071 * <0 - Negative POSIX Error code
1074 int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
1075 struct amdgpu_buffer_size_alignments
1079 * Query firmware versions
1081 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1082 * \param fw_type - \c [in] AMDGPU_INFO_FW_*
1083 * \param ip_instance - \c [in] Index of the IP block of the same type.
1084 * \param index - \c [in] Index of the engine. (for SDMA and MEC)
1085 * \param version - \c [out] Pointer to to the "version" return value
1086 * \param feature - \c [out] Pointer to to the "feature" return value
1088 * \return 0 on success\n
1089 * <0 - Negative POSIX Error code
1092 int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
1093 unsigned ip_instance, unsigned index,
1094 uint32_t *version, uint32_t *feature);
1097 * Query the number of HW IP instances of a certain type.
1099 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1100 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
1101 * \param count - \c [out] Pointer to structure to get information
1103 * \return 0 on success\n
1104 * <0 - Negative POSIX Error code
1106 int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type,
1110 * Query engine information
1112 * This query allows UMD to query information different engines and their
1115 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1116 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
1117 * \param ip_instance - \c [in] Index of the IP block of the same type.
1118 * \param info - \c [out] Pointer to structure to get information
1120 * \return 0 on success\n
1121 * <0 - Negative POSIX Error code
1123 int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
1124 unsigned ip_instance,
1125 struct drm_amdgpu_info_hw_ip *info);
1128 * Query heap information
1130 * This query allows UMD to query potentially available memory resources and
1131 * adjust their logic if necessary.
1133 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1134 * \param heap - \c [in] Heap type
1135 * \param info - \c [in] Pointer to structure to get needed information
1137 * \return 0 on success\n
1138 * <0 - Negative POSIX Error code
1141 int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap,
1142 uint32_t flags, struct amdgpu_heap_info *info);
1145 * Get the CRTC ID from the mode object ID
1147 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1148 * \param id - \c [in] Mode object ID
1149 * \param result - \c [in] Pointer to the CRTC ID
1151 * \return 0 on success\n
1152 * <0 - Negative POSIX Error code
1155 int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
1159 * Query GPU H/w Info
1161 * Query hardware specific information
1163 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1164 * \param heap - \c [in] Heap type
1165 * \param info - \c [in] Pointer to structure to get needed information
1167 * \return 0 on success\n
1168 * <0 - Negative POSIX Error code
1171 int amdgpu_query_gpu_info(amdgpu_device_handle dev,
1172 struct amdgpu_gpu_info *info);
1175 * Query hardware or driver information.
1177 * The return size is query-specific and depends on the "info_id" parameter.
1178 * No more than "size" bytes is returned.
1180 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1181 * \param info_id - \c [in] AMDGPU_INFO_*
1182 * \param size - \c [in] Size of the returned value.
1183 * \param value - \c [out] Pointer to the return value.
1185 * \return 0 on success\n
1186 * <0 - Negative POSIX error code
1189 int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
1190 unsigned size, void *value);
1193 * Query hardware or driver information.
1195 * The return size is query-specific and depends on the "info_id" parameter.
1196 * No more than "size" bytes is returned.
1198 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1199 * \param info - \c [in] amdgpu_sw_info_*
1200 * \param value - \c [out] Pointer to the return value.
1202 * \return 0 on success\n
1203 * <0 - Negative POSIX error code
1206 int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info,
1210 * Query information about GDS
1212 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1213 * \param gds_info - \c [out] Pointer to structure to get GDS information
1215 * \return 0 on success\n
1216 * <0 - Negative POSIX Error code
1219 int amdgpu_query_gds_info(amdgpu_device_handle dev,
1220 struct amdgpu_gds_resource_info *gds_info);
1223 * Query information about sensor.
1225 * The return size is query-specific and depends on the "sensor_type"
1226 * parameter. No more than "size" bytes is returned.
1228 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1229 * \param sensor_type - \c [in] AMDGPU_INFO_SENSOR_*
1230 * \param size - \c [in] Size of the returned value.
1231 * \param value - \c [out] Pointer to the return value.
1233 * \return 0 on success\n
1234 * <0 - Negative POSIX Error code
1237 int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type,
1238 unsigned size, void *value);
1241 * Query information about video capabilities
1243 * The return sizeof(struct drm_amdgpu_info_video_caps)
1245 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1246 * \param caps_type - \c [in] AMDGPU_INFO_VIDEO_CAPS_DECODE(ENCODE)
1247 * \param size - \c [in] Size of the returned value.
1248 * \param value - \c [out] Pointer to the return value.
1250 * \return 0 on success\n
1251 * <0 - Negative POSIX Error code
1254 int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type,
1255 unsigned size, void *value);
1258 * Read a set of consecutive memory-mapped registers.
1259 * Not all registers are allowed to be read by userspace.
1261 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize(
1262 * \param dword_offset - \c [in] Register offset in dwords
1263 * \param count - \c [in] The number of registers to read starting
1265 * \param instance - \c [in] GRBM_GFX_INDEX selector. It may have other
1266 * uses. Set it to 0xffffffff if unsure.
1267 * \param flags - \c [in] Flags with additional information.
1268 * \param values - \c [out] The pointer to return values.
1270 * \return 0 on success\n
1271 * <0 - Negative POSIX error code
1274 int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
1275 unsigned count, uint32_t instance, uint32_t flags,
1279 * Flag to request VA address range in the 32bit address space
1281 #define AMDGPU_VA_RANGE_32_BIT 0x1
1282 #define AMDGPU_VA_RANGE_HIGH 0x2
1283 #define AMDGPU_VA_RANGE_REPLAYABLE 0x4
1286 * Allocate virtual address range
1288 * \param dev - [in] Device handle. See #amdgpu_device_initialize()
1289 * \param va_range_type - \c [in] Type of MC va range from which to allocate
1290 * \param size - \c [in] Size of range. Size must be correctly* aligned.
1291 * It is client responsibility to correctly aligned size based on the future
1292 * usage of allocated range.
1293 * \param va_base_alignment - \c [in] Overwrite base address alignment
1294 * requirement for GPU VM MC virtual
1295 * address assignment. Must be multiple of size alignments received as
1296 * 'amdgpu_buffer_size_alignments'.
1297 * If 0 use the default one.
1298 * \param va_base_required - \c [in] Specified required va base address.
1299 * If 0 then library choose available one.
1300 * If !0 value will be passed and those value already "in use" then
1301 * corresponding error status will be returned.
1302 * \param va_base_allocated - \c [out] On return: Allocated VA base to be used
1304 * \param va_range_handle - \c [out] On return: Handle assigned to allocation
1305 * \param flags - \c [in] flags for special VA range
1307 * \return 0 on success\n
1308 * >0 - AMD specific error code\n
1309 * <0 - Negative POSIX Error code
1312 * It is client responsibility to correctly handle VA assignments and usage.
1313 * Neither kernel driver nor libdrm_amdpgu are able to prevent and
1314 * detect wrong va assignment.
1316 * It is client responsibility to correctly handle multi-GPU cases and to pass
1317 * the corresponding arrays of all devices handles where corresponding VA will
1321 int amdgpu_va_range_alloc(amdgpu_device_handle dev,
1322 enum amdgpu_gpu_va_range va_range_type,
1324 uint64_t va_base_alignment,
1325 uint64_t va_base_required,
1326 uint64_t *va_base_allocated,
1327 amdgpu_va_handle *va_range_handle,
1331 * Free previously allocated virtual address range
1334 * \param va_range_handle - \c [in] Handle assigned to VA allocation
1336 * \return 0 on success\n
1337 * >0 - AMD specific error code\n
1338 * <0 - Negative POSIX Error code
1341 int amdgpu_va_range_free(amdgpu_va_handle va_range_handle);
1344 * Query virtual address range
1346 * UMD can query GPU VM range supported by each device
1347 * to initialize its own VAM accordingly.
1349 * \param dev - [in] Device handle. See #amdgpu_device_initialize()
1350 * \param type - \c [in] Type of virtual address range
1351 * \param offset - \c [out] Start offset of virtual address range
1352 * \param size - \c [out] Size of virtual address range
1354 * \return 0 on success\n
1355 * <0 - Negative POSIX Error code
1359 int amdgpu_va_range_query(amdgpu_device_handle dev,
1360 enum amdgpu_gpu_va_range type,
1365 * VA mapping/unmapping for the buffer object
1367 * \param bo - \c [in] BO handle
1368 * \param offset - \c [in] Start offset to map
1369 * \param size - \c [in] Size to map
1370 * \param addr - \c [in] Start virtual address.
1371 * \param flags - \c [in] Supported flags for mapping/unmapping
1372 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP
1374 * \return 0 on success\n
1375 * <0 - Negative POSIX Error code
1379 int amdgpu_bo_va_op(amdgpu_bo_handle bo,
1387 * VA mapping/unmapping for a buffer object or PRT region.
1389 * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all
1390 * parameters are treated "raw", i.e. size is not automatically aligned, and
1391 * all flags must be specified explicitly.
1393 * \param dev - \c [in] device handle
1394 * \param bo - \c [in] BO handle (may be NULL)
1395 * \param offset - \c [in] Start offset to map
1396 * \param size - \c [in] Size to map
1397 * \param addr - \c [in] Start virtual address.
1398 * \param flags - \c [in] Supported flags for mapping/unmapping
1399 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP
1401 * \return 0 on success\n
1402 * <0 - Negative POSIX Error code
1406 int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
1407 amdgpu_bo_handle bo,
1417 * \param sem - \c [out] semaphore handle
1419 * \return 0 on success\n
1420 * <0 - Negative POSIX Error code
1423 int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem);
1428 * \param context - \c [in] GPU Context
1429 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
1430 * \param ip_instance - \c [in] Index of the IP block of the same type
1431 * \param ring - \c [in] Specify ring index of the IP
1432 * \param sem - \c [in] semaphore handle
1434 * \return 0 on success\n
1435 * <0 - Negative POSIX Error code
1438 int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
1440 uint32_t ip_instance,
1442 amdgpu_semaphore_handle sem);
1447 * \param context - \c [in] GPU Context
1448 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
1449 * \param ip_instance - \c [in] Index of the IP block of the same type
1450 * \param ring - \c [in] Specify ring index of the IP
1451 * \param sem - \c [in] semaphore handle
1453 * \return 0 on success\n
1454 * <0 - Negative POSIX Error code
1457 int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
1459 uint32_t ip_instance,
1461 amdgpu_semaphore_handle sem);
1466 * \param sem - \c [in] semaphore handle
1468 * \return 0 on success\n
1469 * <0 - Negative POSIX Error code
1472 int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem);
1475 * Get the ASIC marketing name
1477 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1479 * \return the constant string of the marketing name
1480 * "NULL" means the ASIC is not found
1482 const char *amdgpu_get_marketing_name(amdgpu_device_handle dev);
1485 * Create kernel sync object
1487 * \param dev - \c [in] device handle
1488 * \param flags - \c [in] flags that affect creation
1489 * \param syncobj - \c [out] sync object handle
1491 * \return 0 on success\n
1492 * <0 - Negative POSIX Error code
1495 int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev,
1500 * Create kernel sync object
1502 * \param dev - \c [in] device handle
1503 * \param syncobj - \c [out] sync object handle
1505 * \return 0 on success\n
1506 * <0 - Negative POSIX Error code
1509 int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
1512 * Destroy kernel sync object
1514 * \param dev - \c [in] device handle
1515 * \param syncobj - \c [in] sync object handle
1517 * \return 0 on success\n
1518 * <0 - Negative POSIX Error code
1521 int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
1525 * Reset kernel sync objects to unsignalled state.
1527 * \param dev - \c [in] device handle
1528 * \param syncobjs - \c [in] array of sync object handles
1529 * \param syncobj_count - \c [in] number of handles in syncobjs
1531 * \return 0 on success\n
1532 * <0 - Negative POSIX Error code
1535 int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev,
1536 const uint32_t *syncobjs, uint32_t syncobj_count);
1539 * Signal kernel sync objects.
1541 * \param dev - \c [in] device handle
1542 * \param syncobjs - \c [in] array of sync object handles
1543 * \param syncobj_count - \c [in] number of handles in syncobjs
1545 * \return 0 on success\n
1546 * <0 - Negative POSIX Error code
1549 int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev,
1550 const uint32_t *syncobjs, uint32_t syncobj_count);
1553 * Signal kernel timeline sync objects.
1555 * \param dev - \c [in] device handle
1556 * \param syncobjs - \c [in] array of sync object handles
1557 * \param points - \c [in] array of timeline points
1558 * \param syncobj_count - \c [in] number of handles in syncobjs
1560 * \return 0 on success\n
1561 * <0 - Negative POSIX Error code
1564 int amdgpu_cs_syncobj_timeline_signal(amdgpu_device_handle dev,
1565 const uint32_t *syncobjs,
1567 uint32_t syncobj_count);
1570 * Wait for one or all sync objects to signal.
1572 * \param dev - \c [in] self-explanatory
1573 * \param handles - \c [in] array of sync object handles
1574 * \param num_handles - \c [in] self-explanatory
1575 * \param timeout_nsec - \c [in] self-explanatory
1576 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_*
1577 * \param first_signaled - \c [in] self-explanatory
1579 * \return 0 on success\n
1581 * <0 - Negative POSIX Error code
1584 int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
1585 uint32_t *handles, unsigned num_handles,
1586 int64_t timeout_nsec, unsigned flags,
1587 uint32_t *first_signaled);
1590 * Wait for one or all sync objects on their points to signal.
1592 * \param dev - \c [in] self-explanatory
1593 * \param handles - \c [in] array of sync object handles
1594 * \param points - \c [in] array of sync points to wait
1595 * \param num_handles - \c [in] self-explanatory
1596 * \param timeout_nsec - \c [in] self-explanatory
1597 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_*
1598 * \param first_signaled - \c [in] self-explanatory
1600 * \return 0 on success\n
1602 * <0 - Negative POSIX Error code
1605 int amdgpu_cs_syncobj_timeline_wait(amdgpu_device_handle dev,
1606 uint32_t *handles, uint64_t *points,
1607 unsigned num_handles,
1608 int64_t timeout_nsec, unsigned flags,
1609 uint32_t *first_signaled);
1611 * Query sync objects payloads.
1613 * \param dev - \c [in] self-explanatory
1614 * \param handles - \c [in] array of sync object handles
1615 * \param points - \c [out] array of sync points returned, which presents
1617 * \param num_handles - \c [in] self-explanatory
1619 * \return 0 on success\n
1621 * <0 - Negative POSIX Error code
1624 int amdgpu_cs_syncobj_query(amdgpu_device_handle dev,
1625 uint32_t *handles, uint64_t *points,
1626 unsigned num_handles);
1628 * Query sync objects last signaled or submitted point.
1630 * \param dev - \c [in] self-explanatory
1631 * \param handles - \c [in] array of sync object handles
1632 * \param points - \c [out] array of sync points returned, which presents
1634 * \param num_handles - \c [in] self-explanatory
1635 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_QUERY_FLAGS_*
1637 * \return 0 on success\n
1639 * <0 - Negative POSIX Error code
1642 int amdgpu_cs_syncobj_query2(amdgpu_device_handle dev,
1643 uint32_t *handles, uint64_t *points,
1644 unsigned num_handles, uint32_t flags);
1647 * Export kernel sync object to shareable fd.
1649 * \param dev - \c [in] device handle
1650 * \param syncobj - \c [in] sync object handle
1651 * \param shared_fd - \c [out] shared file descriptor.
1653 * \return 0 on success\n
1654 * <0 - Negative POSIX Error code
1657 int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
1661 * Import kernel sync object from shareable fd.
1663 * \param dev - \c [in] device handle
1664 * \param shared_fd - \c [in] shared file descriptor.
1665 * \param syncobj - \c [out] sync object handle
1667 * \return 0 on success\n
1668 * <0 - Negative POSIX Error code
1671 int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
1676 * Export kernel sync object to a sync_file.
1678 * \param dev - \c [in] device handle
1679 * \param syncobj - \c [in] sync object handle
1680 * \param sync_file_fd - \c [out] sync_file file descriptor.
1682 * \return 0 on success\n
1683 * <0 - Negative POSIX Error code
1686 int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
1691 * Import kernel sync object from a sync_file.
1693 * \param dev - \c [in] device handle
1694 * \param syncobj - \c [in] sync object handle
1695 * \param sync_file_fd - \c [in] sync_file file descriptor.
1697 * \return 0 on success\n
1698 * <0 - Negative POSIX Error code
1701 int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
1705 * Export kernel timeline sync object to a sync_file.
1707 * \param dev - \c [in] device handle
1708 * \param syncobj - \c [in] sync object handle
1709 * \param point - \c [in] timeline point
1710 * \param flags - \c [in] flags
1711 * \param sync_file_fd - \c [out] sync_file file descriptor.
1713 * \return 0 on success\n
1714 * <0 - Negative POSIX Error code
1717 int amdgpu_cs_syncobj_export_sync_file2(amdgpu_device_handle dev,
1724 * Import kernel timeline sync object from a sync_file.
1726 * \param dev - \c [in] device handle
1727 * \param syncobj - \c [in] sync object handle
1728 * \param point - \c [in] timeline point
1729 * \param sync_file_fd - \c [in] sync_file file descriptor.
1731 * \return 0 on success\n
1732 * <0 - Negative POSIX Error code
1735 int amdgpu_cs_syncobj_import_sync_file2(amdgpu_device_handle dev,
1741 * transfer between syncbojs.
1743 * \param dev - \c [in] device handle
1744 * \param dst_handle - \c [in] sync object handle
1745 * \param dst_point - \c [in] timeline point, 0 presents dst is binary
1746 * \param src_handle - \c [in] sync object handle
1747 * \param src_point - \c [in] timeline point, 0 presents src is binary
1748 * \param flags - \c [in] flags
1750 * \return 0 on success\n
1751 * <0 - Negative POSIX Error code
1754 int amdgpu_cs_syncobj_transfer(amdgpu_device_handle dev,
1755 uint32_t dst_handle,
1757 uint32_t src_handle,
1762 * Export an amdgpu fence as a handle (syncobj or fd).
1764 * \param what AMDGPU_FENCE_TO_HANDLE_GET_{SYNCOBJ, FD}
1765 * \param out_handle returned handle
1767 * \return 0 on success\n
1768 * <0 - Negative POSIX Error code
1770 int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
1771 struct amdgpu_cs_fence *fence,
1773 uint32_t *out_handle);
1776 * Submit raw command submission to kernel
1778 * \param dev - \c [in] device handle
1779 * \param context - \c [in] context handle for context id
1780 * \param bo_list_handle - \c [in] request bo list handle (0 for none)
1781 * \param num_chunks - \c [in] number of CS chunks to submit
1782 * \param chunks - \c [in] array of CS chunks
1783 * \param seq_no - \c [out] output sequence number for submission.
1785 * \return 0 on success\n
1786 * <0 - Negative POSIX Error code
1789 struct drm_amdgpu_cs_chunk;
1790 struct drm_amdgpu_cs_chunk_dep;
1791 struct drm_amdgpu_cs_chunk_data;
1793 int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
1794 amdgpu_context_handle context,
1795 amdgpu_bo_list_handle bo_list_handle,
1797 struct drm_amdgpu_cs_chunk *chunks,
1801 * Submit raw command submission to the kernel with a raw BO list handle.
1803 * \param dev - \c [in] device handle
1804 * \param context - \c [in] context handle for context id
1805 * \param bo_list_handle - \c [in] raw bo list handle (0 for none)
1806 * \param num_chunks - \c [in] number of CS chunks to submit
1807 * \param chunks - \c [in] array of CS chunks
1808 * \param seq_no - \c [out] output sequence number for submission.
1810 * \return 0 on success\n
1811 * <0 - Negative POSIX Error code
1813 * \sa amdgpu_bo_list_create_raw(), amdgpu_bo_list_destroy_raw()
1815 int amdgpu_cs_submit_raw2(amdgpu_device_handle dev,
1816 amdgpu_context_handle context,
1817 uint32_t bo_list_handle,
1819 struct drm_amdgpu_cs_chunk *chunks,
1822 void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
1823 struct drm_amdgpu_cs_chunk_dep *dep);
1824 void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
1825 struct drm_amdgpu_cs_chunk_data *data);
1829 * \param context - \c [in] GPU Context
1830 * \param flags - \c [in] TBD
1832 * \return 0 on success otherwise POSIX Error code
1834 int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags);
1837 * Free reserved VMID
1838 * \param context - \c [in] GPU Context
1839 * \param flags - \c [in] TBD
1841 * \return 0 on success otherwise POSIX Error code
1843 int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, uint32_t flags);
1848 #endif /* #ifdef _AMDGPU_H_ */