Intel/identify-family6-extended.c

   1 /*
   2  *  (C) 2001,2008 Dave Jones.
   3  *
   4  *  Licensed under the terms of the GNU GPL License version 2.
   5  *
   6  *  Intel family 6 specific decoding (Core family).
   7  *  All the CPUs described in this file have cpu->emodel set to 1
   8  */
   9
  10 #include <stdio.h>
  11 #include <string.h>
  12 #include "../x86info.h"
  13 #include "Intel.h"
  14
  15 static char nehalem_info_url[] = "http://www.intel.com/design/corei7/documentation.htm";
  16
  17 static char *intel_nameptr;
  18 #define add_to_cpuname(x)   intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x)
  19
  20 void Identify_Intel_family6core(struct cpudata *cpu)
  21 {
  22         intel_nameptr = cpu->name;
  23
  24         switch (model(cpu)) {
  25         case 7:
  26                 switch (cpu->stepping) {
  27                 case 6:
  28                         // sSpec step CoreFreq Bus cache
  29                         // SLAN3  C0  3.00    1333  12MB (2x6) QX9650
  30                         // SLANY  C0  3.2     1600  12MB (2x6) QX9775
  31 /*
  32 sSpec name  package step HFM/LFM/SLFM FSB  IDAT L2Cache
  33 SLAQG T9300 m-FCPGA C-0  2.5/1.2/0.8   800  2.7 6
  34 SLAPV T9300 m-FCBGA C-0  2.5/1.2/0.8   800  2.7 6
  35 SLAPU T8300 m-FCBGA C-0  2.4/1.2/0.8   800  2.6 3
  36 SLAUU T8100 m-FCPGA C-0  2.1/1.2/0.8   800  2.3 3
  37 SLAPT T8100 m-FCBGA C-0  2.1/1.2/0.8   800  2.3 3
  38 SLAPT T8100 m-FCBGA C-0  2.1/1.2/0.8   800  2.3 3
  39 SLAPA T8300 m-FCPGA M-0  2.4/1.2/0.8   800  2.6 3
  40 SLAPR T8300 m-FCBGA M-0  2.4/1.2/0.8   800  2.6 3
  41 SLAP9 T8100 m-FCPGA M-0  2.1/1.2/0.8   800  2.3 3
  42 SLAPS T8100 m-FCBGA M-0  2.1/1.2/0.8   800  2.3 3
  43 SLAVJ T8100 m-FCPGA M-0  2.1/1.2/0.8   800  2.3 3
  44 SLAXG T8100 m-FCPGA M-0  2.1/1.2/0.8   800  2.3 3
  45 SLAZD T8100 m-FCPGA M-0  2.1/1.2/0.8   800  2.3 3
  46 SLAYZ T8100 m-FCPGA M-0  2.1/1.2/0.8   800  2.3 3
  47 SLAZC T8300 m-FCPGA M-0  2.4/1.2/0.8   800  2.6 3
  48 SLAZB T9300 m-FCPGA C-0  2.5/1.2/0.8   800  2.7 6
  49 SLAYY T9300 m-FCPGA C-0  2.5/1.2/0.8   800  2.7 6
  50 SLAZA T9500 m-FCPGA C-0  2.6/1.2/0.8   800  2.8 6
  51 SLAYX T9500 m-FCPGA C-0  2.6/1.2/0.8   800  2.8 6
  52 SLAQJ X9000 m-FCPGA C-0  2.8/1.2/0.8   800  N/A 6
  53 SLAZ3 X9000 m-FCPGA C-0  2.8/1.2/0.8   800  N/A 6
  54 SLB47 T9600 m-FCPGA C-0  2.80/1.6/0.8 1066 2.93 6
  55 SLB43 T9600 m-FCBGA C-0  2.80/1.6/0.8 1066 2.93 6
  56 SLB46 T9400 m-FCPGA C-0  2.53/1.6/0.8 1066 2.66 6
  57 SL3BX T9400 m-FCBGA C-0  2.53/1.6/0.8 1066 2.66 6
  58 SLB4E P9500 m-FCPGA C-0  2.53/1.6/0.8 1066 2.66 6
  59 SL3BW P9500 m-FCBGA C-0  2.53/1.6/0.8 1066 2.66 6
  60 SLB3S P8600 m-FCPGA M-0  2.40/1.6/0.8 1066 2.53 3
  61 SLB4N P8600 m-FCBGA M-0  2.40/1.6/0.8 1066 2.53 3
  62 SLB3R P8400 m-FCPGA M-0  2.26/1.6/0.8 1066 2.40 3
  63 SLB4M P8400 m-FCBGA M-0  2.26/1.6/0.8 1066 2.40 3
  64 SLB3Q P8400 m-FCPGA M-0  2.26/1.6/0.8 1066 2.40 3
  65 SL3BV P8600 m-FCBGA C-0  2.40/1.6/0.8 1066 2.53 3
  66 SL3BU P8400 m-FCBGA C-0  2.26/1.6/0.8 1066 2.40 3
  67 SLB48 X9100 m-FCPGA C-0  3.06/1.6/0.8 1066 N/A  6
  68 SLAYS T8300 m-FCPGA M-0  2.4/1.2/0.8   800  2.6 3
  69 SLAYU T8100 m-FCPGA M-0  2.1/1.2/0.8   800  2.3 3
  70 SLAYP T8100 m-FCPGA M-0  2.1/1.2/0.8   800  2.3 3
  71 SLAYQ T8300 m-FCPGA M-0  2.4/1.2/0.8   800  2.6 3
  72 SLG8E P7350 m-FCBGA C-0  2.00/1.6/0.8 1066 N/A  3
  73 SLB45 P7450 m-FCPGA C-0  2.13/1.6/0.8 1066 N/A  3
  74 SLB44 P7350 m-FCPGA C-0  2.00/1.6/0.8 1066 N/A  3
  75 SLB54 P7450 m-FCPGA M-0  2.13/1.6/0.8 1066 N/A  3
  76 SLB53 P7350 m-FCPGA M-0  2.00/1.6/0.8 1066 N/A  3
  77 SLB5J QX9300 m-FCPGA E-0 2.53/1.6/(n/a) 1066  2.8 45  12
  78 SLB5G Q9100  m-FCPGA E-0 2.26/1.6/(n/a) 1066 2.53 45  12
  79 SLB64 SP9400 m-FCBGA C-0 2.40/1.6/0.8 1066 2.53 25   6
  80 SLB63 SP9300 m-FCBGA C-0 2.26/1.6/0.8 1066 2.40 25   6
  81 SLB66 SL9400 m-FCBGA C-0 1.86/1.6/0.8 1066 2.13 17   6
  82 SLB65 SL9300 m-FCBGA C-0 1.60/0.8/0.8 1066 1.86 17   6
  83 SLB5V SU9400 m-FCBGA M-0 1.40/0.8/0.8  800 1.60 10  3
  84 SLB5Q SU9300 m-FCBGA M-0 1.20/0.8/0.8  800 1.40 10   3
  85 SLGAR SU3300 m-FCBGA M-0 1.20/0.8/(n/a) 800 N/A  5.5  3    (Celeron)
  86 SLGAS   723  m-FCBGA M-0 1.20/(n/a)/(n/a) 800 N/A  10   1    (Celeron)
  87
  88 */
  89
  90                         add_to_cpuname("Core 2 quad ");
  91                         switch (cpu->MHz) {
  92                         case 3000:      add_to_cpuname("Core 2 quad (QX9650) ");
  93                                 break;
  94                         case 3200:      add_to_cpuname("Core 2 Extreme quad (QX9775) ");
  95                                 break;
  96                         }
  97                         add_to_cpuname("[C0] ");
  98                         break;
  99                 case 7:
 100                         // sSpec step CoreFreq Bus cache
 101                         // SLAWM C1   3.2    1600  12MB (2x6)   QX9770
 102                         // SLAWQ C1   2.83   1600  12MB (2x6)   Q9550
 103                         // SLAWR C1   2.66   1333  12MB (2x6)   Q9450
 104                         // SLAWE M1   2.50   1333  6MB (2x3)    Q9300
 105                         // SLB5M M1   2.33   1333  4MB (2x2)    Q8200
 106                         add_to_cpuname("Core 2 quad ");
 107                         switch (cpu->MHz) {
 108                         case 3200:      add_to_cpuname("(QX9770) [C1] ");
 109                                         break;
 110                         case 2830:      add_to_cpuname("(Q9550) [C1] ");
 111                                         break;
 112                         case 2660:      add_to_cpuname("(Q9450) [C1] ");
 113                                         break;
 114                         case 2500:      add_to_cpuname("(Q9300) [M1] ");
 115                                         break;
 116                         case 2330:      add_to_cpuname("(Q8200) [M1] ");
 117                                         break;
 118                         }
 119                         break;
 120                 case 0xa:
 121                         // sSpec step CoreFreq Bus cache
 122                         // SLB8W E0  3.00     1333 12MB (2x6) Q9650
 123                         // SLB8V E0  2.83     1333 12MB (2x6) Q9550
 124                         // SLB6B R0  2.66     1333 6MB  (2x3) Q9400
 125                         // SLB5W R0  2.5      1333 4MB  (2x2) Q8300
 126                         add_to_cpuname("Core 2 quad ");
 127                         switch (cpu->MHz) {
 128                         case 3000:      add_to_cpuname("(Q9650) [E0] ");
 129                                         break;
 130                         case 2830:      add_to_cpuname("(Q9550) [E0] ");
 131                                         break;
 132                         case 2660:      add_to_cpuname("(Q9400) [R0] ");
 133                                         break;
 134                         case 2500:      add_to_cpuname("(Q8300) [R0] ");
 135                                         break;
 136                         }
 137                         break;
 138                 }
 139                 break;
 140         case 0xa:
 141                 add_to_cpuname("Core i7 ");
 142                 //sSpec step CoreFreq/QuickpathGTs/DDR3 cache
 143                 //SLBCJ C-0     3.2/6.40/1066           8MB
 144                 //SLBCK C-0     2.93/4.80/1066          8MB
 145                 //SLBCH C-0     2.66/4.80/1066          8MB
 146                 break;
 147         case 0xc:
 148                 add_to_cpuname("Atom ");
 149                 switch (cpu->stepping) {
 150                 case 1:
 151                         /*
 152                          * sSpec step TDP Name FSB EFMS  HFM    LFM    Package  MCU
 153                          * QDTD  B0   2.5   x  533 106C1 1.6GHz 800MHz FCBGA8 M01106C1109
 154                          * QDTB  B0   2.5   x  533 106C1 1.6GHz 800MHz FCBGA8 M01106C1109
 155                          * QGFD1 B0     X   X  533 106C1 1.33GHz ----  FCBGA437 M01106C1109
 156                          */
 157                         break;
 158                 case 2:
 159                         /*
 160                          * sSpec step TDP Name FSB EFMS  HFM     LFM    Package
 161                          *
 162                          *
 163                          * SLB6Q C0 0.65W Z500 400 106C2 800GHz  600MHz FCBGA8
 164                          * SLB2C C0    2W Z510 400 106C2 1.1GHz  600MHz FCBGA8
 165                          * SLGMG C0 0.65W Z515 400 106C2 800MHz  600MHz FCBGA8
 166                          * SLB2H C0    2W Z520 533 106C2 1.33GHz 800MHz FCBGA8
 167                          * SLB6P C0    2W Z530 533 106C2 1.60GHz 800MHz FCBGA8
 168                          * QGZT  C0  2.5W N270 533 106C2 1.60GHz 800MHz FCBGA8
 169                          * QKGY1 C0    8W  300 533 106C2 1.60GHz ------ FCBGA437
 170                          * QGZR2 C0    4W  230 533 106C2 1.60GHz -----  FCBGA437
 171                          * SLB2M C0  2.4W Z540 533 106C2 1.86GHz 800MHz FCBGA8
 172                          * SLGPT C0  2.4W Z550 533 106C2 2.0GHz  800MHz FCBGA8
 173                          */
 174                         switch (cpu->MHz) {
 175                         case 800:       add_to_cpuname("Z500/Z515 [SLB6Q/SLGMG][C0]");
 176                                         break;
 177                         case 1100:      add_to_cpuname("Z510 [SLB2C][C0]");
 178                                         break;
 179                         case 1330:      add_to_cpuname("Z520 [SLB2H][C0]");
 180                                         break;
 181                         case 1600:      // could be a Z530,an N270,a QKGY1 or a QGZR2
 182                                         break;
 183                         case 1860:      add_to_cpuname("Z540 [SLB2M][C0]");
 184                                         break;
 185                         case 2000:      add_to_cpuname("Z550 [SLGPT][C0]");
 186                                         break;
 187                         }
 188                         break;
 189                 }
 190                 break;
 191         case 0xe:
 192                 add_to_cpuname("Core ");
 193                 switch (cpu->stepping) {
 194                 case 8:
 195                         switch (cpu->MHz) {
 196                         case 1000:
 197                                 // SL99W/SL8W7 533FSB
 198                                 add_to_cpuname("Duo U2400/Solo U1300 [C-0]");
 199                                 break;
 200                         case 1200:
 201                                 // SL8W6 533FSB
 202                                 add_to_cpuname("Solo U1400 [C-0]");
 203                                 break;
 204                         case 1500:
 205                                 // SL8VX 667FSB
 206                                 add_to_cpuname("Duo L2300 [C-0]");
 207                                 break;
 208                         case 1600:
 209                                 // SL9JE/SL9JV/SL8VR/SL8VV/SL8VY/SL8W3/SL8VW 667FSB
 210                                 add_to_cpuname("Solo T1300/Duo T2300(E)/Duo L2400");
 211                                 break;
 212                         case 1800:
 213                                 // SL92X/SL8VQ/SL8VU/SL92V/SL92X 667FSB
 214                                 add_to_cpuname("Solo T1400/Duo T2400 [C-0]");
 215                                 break;
 216                         case 2000:
 217                                 // SL8VP/SL8VT/SL92U/SL92W 667FSB
 218                                 add_to_cpuname("Solo T1500/Duo T2500 [C-0]");
 219                                 break;
 220                         case 2150:
 221                                 // SL8VN/SL8VS 667FSB
 222                                 add_to_cpuname("Duo T2600 [C-0]");
 223                                 break;
 224                         }
 225                         break;
 226                 case 0xc:
 227                         switch (cpu->MHz) {
 228                         case 1200:
 229                                 // SL99V 533FSB
 230                                 add_to_cpuname("Duo U2500 [D-0]");
 231                                 break;
 232                         case 1800:
 233                                 // SL9JU 667FSB
 234                                 add_to_cpuname("Duo L2500 [D-0]");
 235                                 break;
 236                         case 2300:
 237                                 // SL9JP/SL9K4 667FSB
 238                                 add_to_cpuname("Duo T2700 [D-0]");
 239                                 break;
 240                         }
 241                 }
 242                 break;
 243
 244         case 0x17:
 245                 add_to_cpuname("Core 2 Duo ");
 246                 switch (cpu->stepping) {
 247                 case 4: add_to_cpuname("(Penryn)");
 248                         break;
 249                 case 6: add_to_cpuname("P8600");
 250                         break;
 251                 }
 252                 break;
 253
 254         case 0x1a:
 255                 /*
 256                  * SLBCJ C-0 0x000106A4 3.20 / 6.40/ 1066 8MB
 257                  * SLBCK C-0 0x000106A4 2.93 / 4.80/ 1066 8MB
 258                  * SLBCH C-0 0x000106A4 2.66 / 4.80/ 1066 8MB
 259                  */
 260                 add_to_cpuname("Core i7 (Nehalem) [bloomfield/gainestown]");
 261                 cpu->info_url = strdup(nehalem_info_url);
 262                 switch (cpu->MHz) {
 263                 case 3200:      add_to_cpuname(" [C-0][SLBCJ]");
 264                                 break;
 265                 case 2930:      add_to_cpuname(" [C-0][SLBCK]");
 266                                 break;
 267                 case 2660:      add_to_cpuname(" [C-0][SLBCH]");
 268                                 break;
 269                 }
 270                 break;
 271
 272         case 0x1c:
 273                 add_to_cpuname("Atom");
 274                 switch (cpu->stepping) {
 275                 case 10:        add_to_cpuname(" D510");
 276                                 break;
 277                 }
 278                 break;
 279
 280         case 0x1e:
 281                 add_to_cpuname("Core i7 (Nehalem) [Lynnfield/Clarksfield/Jasper Forest]");
 282                 break;
 283
 284         case 0x25:
 285                 add_to_cpuname("Core i7 (Nehalem) [Clarkdale/Arrandale]");
 286                 break;
 287
 288         case 0x2c:
 289                 add_to_cpuname("Core i7 (Nehalem) [Gulftown/Westmere-EP]");
 290                 break;
 291
 292         case 0x2d:
 293                 add_to_cpuname("Core i7 (Sandybridge) [Romely-EP]");
 294                 break;
 295
 296         case 0x2e:
 297                 add_to_cpuname("Core i7 (Nehalem) [Beckton]");
 298                 break;
 299
 300         case 0x2f:
 301                 add_to_cpuname("Core i7 (Nehalem-EX) [Westmere] [Xeon E7]");
 302                 break;
 303
 304         default:
 305                 add_to_cpuname("Unknown model. ");
 306         }
 307 }