1 ============================
2 LINUX KERNEL MEMORY BARRIERS
3 ============================
5 By: David Howells <dhowells@redhat.com>
6 Paul E. McKenney <paulmck@linux.vnet.ibm.com>
10 (*) Abstract memory access model.
15 (*) What are memory barriers?
17 - Varieties of memory barrier.
18 - What may not be assumed about memory barriers?
19 - Data dependency barriers.
20 - Control dependencies.
21 - SMP barrier pairing.
22 - Examples of memory barrier sequences.
23 - Read memory barriers vs load speculation.
26 (*) Explicit kernel barriers.
29 - CPU memory barriers.
32 (*) Implicit kernel memory barriers.
35 - Interrupt disabling functions.
36 - Sleep and wake-up functions.
37 - Miscellaneous functions.
39 (*) Inter-CPU locking barrier effects.
41 - Locks vs memory accesses.
42 - Locks vs I/O accesses.
44 (*) Where are memory barriers needed?
46 - Interprocessor interaction.
51 (*) Kernel I/O barrier effects.
53 (*) Assumed minimum execution ordering model.
55 (*) The effects of the cpu cache.
58 - Cache coherency vs DMA.
59 - Cache coherency vs MMIO.
61 (*) The things CPUs get up to.
63 - And then there's the Alpha.
72 ============================
73 ABSTRACT MEMORY ACCESS MODEL
74 ============================
76 Consider the following abstract model of the system:
81 +-------+ : +--------+ : +-------+
84 | CPU 1 |<----->| Memory |<----->| CPU 2 |
87 +-------+ : +--------+ : +-------+
95 +---------->| Device |<----------+
101 Each CPU executes a program that generates memory access operations. In the
102 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
103 perform the memory operations in any order it likes, provided program causality
104 appears to be maintained. Similarly, the compiler may also arrange the
105 instructions it emits in any order it likes, provided it doesn't affect the
106 apparent operation of the program.
108 So in the above diagram, the effects of the memory operations performed by a
109 CPU are perceived by the rest of the system as the operations cross the
110 interface between the CPU and rest of the system (the dotted lines).
113 For example, consider the following sequence of events:
116 =============== ===============
121 The set of accesses as seen by the memory system in the middle can be arranged
122 in 24 different combinations:
124 STORE A=3, STORE B=4, x=LOAD A->3, y=LOAD B->4
125 STORE A=3, STORE B=4, y=LOAD B->4, x=LOAD A->3
126 STORE A=3, x=LOAD A->3, STORE B=4, y=LOAD B->4
127 STORE A=3, x=LOAD A->3, y=LOAD B->2, STORE B=4
128 STORE A=3, y=LOAD B->2, STORE B=4, x=LOAD A->3
129 STORE A=3, y=LOAD B->2, x=LOAD A->3, STORE B=4
130 STORE B=4, STORE A=3, x=LOAD A->3, y=LOAD B->4
134 and can thus result in four different combinations of values:
142 Furthermore, the stores committed by a CPU to the memory system may not be
143 perceived by the loads made by another CPU in the same order as the stores were
147 As a further example, consider this sequence of events:
150 =============== ===============
151 { A == 1, B == 2, C = 3, P == &A, Q == &C }
155 There is an obvious data dependency here, as the value loaded into D depends on
156 the address retrieved from P by CPU 2. At the end of the sequence, any of the
157 following results are possible:
159 (Q == &A) and (D == 1)
160 (Q == &B) and (D == 2)
161 (Q == &B) and (D == 4)
163 Note that CPU 2 will never try and load C into D because the CPU will load P
164 into Q before issuing the load of *Q.
170 Some devices present their control interfaces as collections of memory
171 locations, but the order in which the control registers are accessed is very
172 important. For instance, imagine an ethernet card with a set of internal
173 registers that are accessed through an address port register (A) and a data
174 port register (D). To read internal register 5, the following code might then
180 but this might show up as either of the following two sequences:
182 STORE *A = 5, x = LOAD *D
183 x = LOAD *D, STORE *A = 5
185 the second of which will almost certainly result in a malfunction, since it set
186 the address _after_ attempting to read the register.
192 There are some minimal guarantees that may be expected of a CPU:
194 (*) On any given CPU, dependent memory accesses will be issued in order, with
195 respect to itself. This means that for:
197 ACCESS_ONCE(Q) = P; smp_read_barrier_depends(); D = ACCESS_ONCE(*Q);
199 the CPU will issue the following memory operations:
201 Q = LOAD P, D = LOAD *Q
203 and always in that order. On most systems, smp_read_barrier_depends()
204 does nothing, but it is required for DEC Alpha. The ACCESS_ONCE()
205 is required to prevent compiler mischief. Please note that you
206 should normally use something like rcu_dereference() instead of
207 open-coding smp_read_barrier_depends().
209 (*) Overlapping loads and stores within a particular CPU will appear to be
210 ordered within that CPU. This means that for:
212 a = ACCESS_ONCE(*X); ACCESS_ONCE(*X) = b;
214 the CPU will only issue the following sequence of memory operations:
216 a = LOAD *X, STORE *X = b
220 ACCESS_ONCE(*X) = c; d = ACCESS_ONCE(*X);
222 the CPU will only issue:
224 STORE *X = c, d = LOAD *X
226 (Loads and stores overlap if they are targeted at overlapping pieces of
229 And there are a number of things that _must_ or _must_not_ be assumed:
231 (*) It _must_not_ be assumed that the compiler will do what you want with
232 memory references that are not protected by ACCESS_ONCE(). Without
233 ACCESS_ONCE(), the compiler is within its rights to do all sorts
234 of "creative" transformations, which are covered in the Compiler
237 (*) It _must_not_ be assumed that independent loads and stores will be issued
238 in the order given. This means that for:
240 X = *A; Y = *B; *D = Z;
242 we may get any of the following sequences:
244 X = LOAD *A, Y = LOAD *B, STORE *D = Z
245 X = LOAD *A, STORE *D = Z, Y = LOAD *B
246 Y = LOAD *B, X = LOAD *A, STORE *D = Z
247 Y = LOAD *B, STORE *D = Z, X = LOAD *A
248 STORE *D = Z, X = LOAD *A, Y = LOAD *B
249 STORE *D = Z, Y = LOAD *B, X = LOAD *A
251 (*) It _must_ be assumed that overlapping memory accesses may be merged or
252 discarded. This means that for:
254 X = *A; Y = *(A + 4);
256 we may get any one of the following sequences:
258 X = LOAD *A; Y = LOAD *(A + 4);
259 Y = LOAD *(A + 4); X = LOAD *A;
260 {X, Y} = LOAD {*A, *(A + 4) };
264 *A = X; *(A + 4) = Y;
268 STORE *A = X; STORE *(A + 4) = Y;
269 STORE *(A + 4) = Y; STORE *A = X;
270 STORE {*A, *(A + 4) } = {X, Y};
273 =========================
274 WHAT ARE MEMORY BARRIERS?
275 =========================
277 As can be seen above, independent memory operations are effectively performed
278 in random order, but this can be a problem for CPU-CPU interaction and for I/O.
279 What is required is some way of intervening to instruct the compiler and the
280 CPU to restrict the order.
282 Memory barriers are such interventions. They impose a perceived partial
283 ordering over the memory operations on either side of the barrier.
285 Such enforcement is important because the CPUs and other devices in a system
286 can use a variety of tricks to improve performance, including reordering,
287 deferral and combination of memory operations; speculative loads; speculative
288 branch prediction and various types of caching. Memory barriers are used to
289 override or suppress these tricks, allowing the code to sanely control the
290 interaction of multiple CPUs and/or devices.
293 VARIETIES OF MEMORY BARRIER
294 ---------------------------
296 Memory barriers come in four basic varieties:
298 (1) Write (or store) memory barriers.
300 A write memory barrier gives a guarantee that all the STORE operations
301 specified before the barrier will appear to happen before all the STORE
302 operations specified after the barrier with respect to the other
303 components of the system.
305 A write barrier is a partial ordering on stores only; it is not required
306 to have any effect on loads.
308 A CPU can be viewed as committing a sequence of store operations to the
309 memory system as time progresses. All stores before a write barrier will
310 occur in the sequence _before_ all the stores after the write barrier.
312 [!] Note that write barriers should normally be paired with read or data
313 dependency barriers; see the "SMP barrier pairing" subsection.
316 (2) Data dependency barriers.
318 A data dependency barrier is a weaker form of read barrier. In the case
319 where two loads are performed such that the second depends on the result
320 of the first (eg: the first load retrieves the address to which the second
321 load will be directed), a data dependency barrier would be required to
322 make sure that the target of the second load is updated before the address
323 obtained by the first load is accessed.
325 A data dependency barrier is a partial ordering on interdependent loads
326 only; it is not required to have any effect on stores, independent loads
327 or overlapping loads.
329 As mentioned in (1), the other CPUs in the system can be viewed as
330 committing sequences of stores to the memory system that the CPU being
331 considered can then perceive. A data dependency barrier issued by the CPU
332 under consideration guarantees that for any load preceding it, if that
333 load touches one of a sequence of stores from another CPU, then by the
334 time the barrier completes, the effects of all the stores prior to that
335 touched by the load will be perceptible to any loads issued after the data
338 See the "Examples of memory barrier sequences" subsection for diagrams
339 showing the ordering constraints.
341 [!] Note that the first load really has to have a _data_ dependency and
342 not a control dependency. If the address for the second load is dependent
343 on the first load, but the dependency is through a conditional rather than
344 actually loading the address itself, then it's a _control_ dependency and
345 a full read barrier or better is required. See the "Control dependencies"
346 subsection for more information.
348 [!] Note that data dependency barriers should normally be paired with
349 write barriers; see the "SMP barrier pairing" subsection.
352 (3) Read (or load) memory barriers.
354 A read barrier is a data dependency barrier plus a guarantee that all the
355 LOAD operations specified before the barrier will appear to happen before
356 all the LOAD operations specified after the barrier with respect to the
357 other components of the system.
359 A read barrier is a partial ordering on loads only; it is not required to
360 have any effect on stores.
362 Read memory barriers imply data dependency barriers, and so can substitute
365 [!] Note that read barriers should normally be paired with write barriers;
366 see the "SMP barrier pairing" subsection.
369 (4) General memory barriers.
371 A general memory barrier gives a guarantee that all the LOAD and STORE
372 operations specified before the barrier will appear to happen before all
373 the LOAD and STORE operations specified after the barrier with respect to
374 the other components of the system.
376 A general memory barrier is a partial ordering over both loads and stores.
378 General memory barriers imply both read and write memory barriers, and so
379 can substitute for either.
382 And a couple of implicit varieties:
384 (5) ACQUIRE operations.
386 This acts as a one-way permeable barrier. It guarantees that all memory
387 operations after the ACQUIRE operation will appear to happen after the
388 ACQUIRE operation with respect to the other components of the system.
389 ACQUIRE operations include LOCK operations and smp_load_acquire()
392 Memory operations that occur before an ACQUIRE operation may appear to
393 happen after it completes.
395 An ACQUIRE operation should almost always be paired with a RELEASE
399 (6) RELEASE operations.
401 This also acts as a one-way permeable barrier. It guarantees that all
402 memory operations before the RELEASE operation will appear to happen
403 before the RELEASE operation with respect to the other components of the
404 system. RELEASE operations include UNLOCK operations and
405 smp_store_release() operations.
407 Memory operations that occur after a RELEASE operation may appear to
408 happen before it completes.
410 The use of ACQUIRE and RELEASE operations generally precludes the need
411 for other sorts of memory barrier (but note the exceptions mentioned in
412 the subsection "MMIO write barrier"). In addition, a RELEASE+ACQUIRE
413 pair is -not- guaranteed to act as a full memory barrier. However, after
414 an ACQUIRE on a given variable, all memory accesses preceding any prior
415 RELEASE on that same variable are guaranteed to be visible. In other
416 words, within a given variable's critical section, all accesses of all
417 previous critical sections for that variable are guaranteed to have
420 This means that ACQUIRE acts as a minimal "acquire" operation and
421 RELEASE acts as a minimal "release" operation.
424 Memory barriers are only required where there's a possibility of interaction
425 between two CPUs or between a CPU and a device. If it can be guaranteed that
426 there won't be any such interaction in any particular piece of code, then
427 memory barriers are unnecessary in that piece of code.
430 Note that these are the _minimum_ guarantees. Different architectures may give
431 more substantial guarantees, but they may _not_ be relied upon outside of arch
435 WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
436 ----------------------------------------------
438 There are certain things that the Linux kernel memory barriers do not guarantee:
440 (*) There is no guarantee that any of the memory accesses specified before a
441 memory barrier will be _complete_ by the completion of a memory barrier
442 instruction; the barrier can be considered to draw a line in that CPU's
443 access queue that accesses of the appropriate type may not cross.
445 (*) There is no guarantee that issuing a memory barrier on one CPU will have
446 any direct effect on another CPU or any other hardware in the system. The
447 indirect effect will be the order in which the second CPU sees the effects
448 of the first CPU's accesses occur, but see the next point:
450 (*) There is no guarantee that a CPU will see the correct order of effects
451 from a second CPU's accesses, even _if_ the second CPU uses a memory
452 barrier, unless the first CPU _also_ uses a matching memory barrier (see
453 the subsection on "SMP Barrier Pairing").
455 (*) There is no guarantee that some intervening piece of off-the-CPU
456 hardware[*] will not reorder the memory accesses. CPU cache coherency
457 mechanisms should propagate the indirect effects of a memory barrier
458 between CPUs, but might not do so in order.
460 [*] For information on bus mastering DMA and coherency please read:
462 Documentation/PCI/pci.txt
463 Documentation/DMA-API-HOWTO.txt
464 Documentation/DMA-API.txt
467 DATA DEPENDENCY BARRIERS
468 ------------------------
470 The usage requirements of data dependency barriers are a little subtle, and
471 it's not always obvious that they're needed. To illustrate, consider the
472 following sequence of events:
475 =============== ===============
476 { A == 1, B == 2, C = 3, P == &A, Q == &C }
483 There's a clear data dependency here, and it would seem that by the end of the
484 sequence, Q must be either &A or &B, and that:
486 (Q == &A) implies (D == 1)
487 (Q == &B) implies (D == 4)
489 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
490 leading to the following situation:
492 (Q == &B) and (D == 2) ????
494 Whilst this may seem like a failure of coherency or causality maintenance, it
495 isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
498 To deal with this, a data dependency barrier or better must be inserted
499 between the address load and the data load:
502 =============== ===============
503 { A == 1, B == 2, C = 3, P == &A, Q == &C }
508 <data dependency barrier>
511 This enforces the occurrence of one of the two implications, and prevents the
512 third possibility from arising.
514 [!] Note that this extremely counterintuitive situation arises most easily on
515 machines with split caches, so that, for example, one cache bank processes
516 even-numbered cache lines and the other bank processes odd-numbered cache
517 lines. The pointer P might be stored in an odd-numbered cache line, and the
518 variable B might be stored in an even-numbered cache line. Then, if the
519 even-numbered bank of the reading CPU's cache is extremely busy while the
520 odd-numbered bank is idle, one can see the new value of the pointer P (&B),
521 but the old value of the variable B (2).
524 Another example of where data dependency barriers might be required is where a
525 number is read from memory and then used to calculate the index for an array
529 =============== ===============
530 { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
535 <data dependency barrier>
539 The data dependency barrier is very important to the RCU system,
540 for example. See rcu_assign_pointer() and rcu_dereference() in
541 include/linux/rcupdate.h. This permits the current target of an RCU'd
542 pointer to be replaced with a new modified target, without the replacement
543 target appearing to be incompletely initialised.
545 See also the subsection on "Cache Coherency" for a more thorough example.
551 A control dependency requires a full read memory barrier, not simply a data
552 dependency barrier to make it work correctly. Consider the following bit of
557 <data dependency barrier> /* BUG: No data dependency!!! */
561 This will not have the desired effect because there is no actual data
562 dependency, but rather a control dependency that the CPU may short-circuit
563 by attempting to predict the outcome in advance, so that other CPUs see
564 the load from b as having happened before the load from a. In such a
565 case what's actually required is:
573 However, stores are not speculated. This means that ordering -is- provided
574 in the following example:
577 if (ACCESS_ONCE(q)) {
581 Please note that ACCESS_ONCE() is not optional! Without the ACCESS_ONCE(),
582 the compiler is within its rights to transform this example:
586 b = p; /* BUG: Compiler can reorder!!! */
589 b = p; /* BUG: Compiler can reorder!!! */
593 into this, which of course defeats the ordering:
602 Worse yet, if the compiler is able to prove (say) that the value of
603 variable 'a' is always non-zero, it would be well within its rights
604 to optimize the original example by eliminating the "if" statement
608 b = p; /* BUG: Compiler can reorder!!! */
611 The solution is again ACCESS_ONCE(), which preserves the ordering between
612 the load from variable 'a' and the store to variable 'b':
623 You could also use barrier() to prevent the compiler from moving
624 the stores to variable 'b', but barrier() would not prevent the
625 compiler from proving to itself that a==1 always, so ACCESS_ONCE()
628 It is important to note that control dependencies absolutely require a
629 a conditional. For example, the following "optimized" version of
630 the above example breaks ordering:
633 ACCESS_ONCE(b) = p; /* BUG: No ordering vs. load from a!!! */
635 /* ACCESS_ONCE(b) = p; -- moved up, BUG!!! */
638 /* ACCESS_ONCE(b) = p; -- moved up, BUG!!! */
642 It is of course legal for the prior load to be part of the conditional,
643 for example, as follows:
645 if (ACCESS_ONCE(a) > 0) {
646 ACCESS_ONCE(b) = q / 2;
649 ACCESS_ONCE(b) = q / 3;
653 This will again ensure that the load from variable 'a' is ordered before the
654 stores to variable 'b'.
656 In addition, you need to be careful what you do with the local variable 'q',
657 otherwise the compiler might be able to guess the value and again remove
658 the needed conditional. For example:
669 If MAX is defined to be 1, then the compiler knows that (q % MAX) is
670 equal to zero, in which case the compiler is within its rights to
671 transform the above code into the following:
677 This transformation loses the ordering between the load from variable 'a'
678 and the store to variable 'b'. If you are relying on this ordering, you
679 should do something like the following:
682 BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */
691 Finally, control dependencies do -not- provide transitivity. This is
692 demonstrated by two related examples:
695 ===================== =====================
696 r1 = ACCESS_ONCE(x); r2 = ACCESS_ONCE(y);
697 if (r1 >= 0) if (r2 >= 0)
698 ACCESS_ONCE(y) = 1; ACCESS_ONCE(x) = 1;
700 assert(!(r1 == 1 && r2 == 1));
702 The above two-CPU example will never trigger the assert(). However,
703 if control dependencies guaranteed transitivity (which they do not),
704 then adding the following two CPUs would guarantee a related assertion:
707 ===================== =====================
708 ACCESS_ONCE(x) = 2; ACCESS_ONCE(y) = 2;
710 assert(!(r1 == 2 && r2 == 2 && x == 1 && y == 1)); /* FAILS!!! */
712 But because control dependencies do -not- provide transitivity, the
713 above assertion can fail after the combined four-CPU example completes.
714 If you need the four-CPU example to provide ordering, you will need
715 smp_mb() between the loads and stores in the CPU 0 and CPU 1 code fragments.
719 (*) Control dependencies can order prior loads against later stores.
720 However, they do -not- guarantee any other sort of ordering:
721 Not prior loads against later loads, nor prior stores against
722 later anything. If you need these other forms of ordering,
723 use smb_rmb(), smp_wmb(), or, in the case of prior stores and
724 later loads, smp_mb().
726 (*) Control dependencies require at least one run-time conditional
727 between the prior load and the subsequent store. If the compiler
728 is able to optimize the conditional away, it will have also
729 optimized away the ordering. Careful use of ACCESS_ONCE() can
730 help to preserve the needed conditional.
732 (*) Control dependencies require that the compiler avoid reordering the
733 dependency into nonexistence. Careful use of ACCESS_ONCE() or
734 barrier() can help to preserve your control dependency. Please
735 see the Compiler Barrier section for more information.
737 (*) Control dependencies do -not- provide transitivity. If you
738 need transitivity, use smp_mb().
744 When dealing with CPU-CPU interactions, certain types of memory barrier should
745 always be paired. A lack of appropriate pairing is almost certainly an error.
747 A write barrier should always be paired with a data dependency barrier or read
748 barrier, though a general barrier would also be viable. Similarly a read
749 barrier or a data dependency barrier should always be paired with at least an
750 write barrier, though, again, a general barrier is viable:
753 =============== ===============
756 ACCESS_ONCE(b) = 2; x = ACCESS_ONCE(b);
763 =============== ===============================
766 ACCESS_ONCE(b) = &a; x = ACCESS_ONCE(b);
767 <data dependency barrier>
770 Basically, the read barrier always has to be there, even though it can be of
773 [!] Note that the stores before the write barrier would normally be expected to
774 match the loads after the read barrier or the data dependency barrier, and vice
778 =================== ===================
779 ACCESS_ONCE(a) = 1; }---- --->{ v = ACCESS_ONCE(c);
780 ACCESS_ONCE(b) = 2; } \ / { w = ACCESS_ONCE(d);
781 <write barrier> \ <read barrier>
782 ACCESS_ONCE(c) = 3; } / \ { x = ACCESS_ONCE(a);
783 ACCESS_ONCE(d) = 4; }---- --->{ y = ACCESS_ONCE(b);
786 EXAMPLES OF MEMORY BARRIER SEQUENCES
787 ------------------------------------
789 Firstly, write barriers act as partial orderings on store operations.
790 Consider the following sequence of events:
793 =======================
801 This sequence of events is committed to the memory coherence system in an order
802 that the rest of the system might perceive as the unordered set of { STORE A,
803 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
808 | |------>| C=3 | } /\
809 | | : +------+ }----- \ -----> Events perceptible to
810 | | : | A=1 | } \/ the rest of the system
812 | CPU 1 | : | B=2 | }
814 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
815 | | +------+ } requires all stores prior to the
816 | | : | E=5 | } barrier to be committed before
817 | | : +------+ } further stores may take place
822 | Sequence in which stores are committed to the
823 | memory system by CPU 1
827 Secondly, data dependency barriers act as partial orderings on data-dependent
828 loads. Consider the following sequence of events:
831 ======================= =======================
832 { B = 7; X = 9; Y = 8; C = &Y }
837 STORE D = 4 LOAD C (gets &B)
840 Without intervention, CPU 2 may perceive the events on CPU 1 in some
841 effectively random order, despite the write barrier issued by CPU 1:
844 | | +------+ +-------+ | Sequence of update
845 | |------>| B=2 |----- --->| Y->8 | | of perception on
846 | | : +------+ \ +-------+ | CPU 2
847 | CPU 1 | : | A=1 | \ --->| C->&Y | V
848 | | +------+ | +-------+
849 | | wwwwwwwwwwwwwwww | : :
851 | | : | C=&B |--- | : : +-------+
852 | | : +------+ \ | +-------+ | |
853 | |------>| D=4 | ----------->| C->&B |------>| |
854 | | +------+ | +-------+ | |
855 +-------+ : : | : : | |
859 Apparently incorrect ---> | | B->7 |------>| |
860 perception of B (!) | +-------+ | |
863 The load of X holds ---> \ | X->9 |------>| |
864 up the maintenance \ +-------+ | |
865 of coherence of B ----->| B->2 | +-------+
870 In the above example, CPU 2 perceives that B is 7, despite the load of *C
871 (which would be B) coming after the LOAD of C.
873 If, however, a data dependency barrier were to be placed between the load of C
874 and the load of *C (ie: B) on CPU 2:
877 ======================= =======================
878 { B = 7; X = 9; Y = 8; C = &Y }
883 STORE D = 4 LOAD C (gets &B)
884 <data dependency barrier>
887 then the following will occur:
890 | | +------+ +-------+
891 | |------>| B=2 |----- --->| Y->8 |
892 | | : +------+ \ +-------+
893 | CPU 1 | : | A=1 | \ --->| C->&Y |
894 | | +------+ | +-------+
895 | | wwwwwwwwwwwwwwww | : :
897 | | : | C=&B |--- | : : +-------+
898 | | : +------+ \ | +-------+ | |
899 | |------>| D=4 | ----------->| C->&B |------>| |
900 | | +------+ | +-------+ | |
901 +-------+ : : | : : | |
907 Makes sure all effects ---> \ ddddddddddddddddd | |
908 prior to the store of C \ +-------+ | |
909 are perceptible to ----->| B->2 |------>| |
910 subsequent loads +-------+ | |
914 And thirdly, a read barrier acts as a partial order on loads. Consider the
915 following sequence of events:
918 ======================= =======================
926 Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
927 some effectively random order, despite the write barrier issued by CPU 1:
930 | | +------+ +-------+
931 | |------>| A=1 |------ --->| A->0 |
932 | | +------+ \ +-------+
933 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
934 | | +------+ | +-------+
935 | |------>| B=2 |--- | : :
936 | | +------+ \ | : : +-------+
937 +-------+ : : \ | +-------+ | |
938 ---------->| B->2 |------>| |
939 | +-------+ | CPU 2 |
950 If, however, a read barrier were to be placed between the load of B and the
954 ======================= =======================
963 then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
967 | | +------+ +-------+
968 | |------>| A=1 |------ --->| A->0 |
969 | | +------+ \ +-------+
970 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
971 | | +------+ | +-------+
972 | |------>| B=2 |--- | : :
973 | | +------+ \ | : : +-------+
974 +-------+ : : \ | +-------+ | |
975 ---------->| B->2 |------>| |
976 | +-------+ | CPU 2 |
979 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
980 barrier causes all effects \ +-------+ | |
981 prior to the storage of B ---->| A->1 |------>| |
982 to be perceptible to CPU 2 +-------+ | |
986 To illustrate this more completely, consider what could happen if the code
987 contained a load of A either side of the read barrier:
990 ======================= =======================
996 LOAD A [first load of A]
998 LOAD A [second load of A]
1000 Even though the two loads of A both occur after the load of B, they may both
1001 come up with different values:
1004 | | +------+ +-------+
1005 | |------>| A=1 |------ --->| A->0 |
1006 | | +------+ \ +-------+
1007 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1008 | | +------+ | +-------+
1009 | |------>| B=2 |--- | : :
1010 | | +------+ \ | : : +-------+
1011 +-------+ : : \ | +-------+ | |
1012 ---------->| B->2 |------>| |
1013 | +-------+ | CPU 2 |
1017 | | A->0 |------>| 1st |
1019 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1020 barrier causes all effects \ +-------+ | |
1021 prior to the storage of B ---->| A->1 |------>| 2nd |
1022 to be perceptible to CPU 2 +-------+ | |
1026 But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1027 before the read barrier completes anyway:
1030 | | +------+ +-------+
1031 | |------>| A=1 |------ --->| A->0 |
1032 | | +------+ \ +-------+
1033 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1034 | | +------+ | +-------+
1035 | |------>| B=2 |--- | : :
1036 | | +------+ \ | : : +-------+
1037 +-------+ : : \ | +-------+ | |
1038 ---------->| B->2 |------>| |
1039 | +-------+ | CPU 2 |
1043 ---->| A->1 |------>| 1st |
1045 rrrrrrrrrrrrrrrrr | |
1047 | A->1 |------>| 2nd |
1052 The guarantee is that the second load will always come up with A == 1 if the
1053 load of B came up with B == 2. No such guarantee exists for the first load of
1054 A; that may come up with either A == 0 or A == 1.
1057 READ MEMORY BARRIERS VS LOAD SPECULATION
1058 ----------------------------------------
1060 Many CPUs speculate with loads: that is they see that they will need to load an
1061 item from memory, and they find a time where they're not using the bus for any
1062 other loads, and so do the load in advance - even though they haven't actually
1063 got to that point in the instruction execution flow yet. This permits the
1064 actual load instruction to potentially complete immediately because the CPU
1065 already has the value to hand.
1067 It may turn out that the CPU didn't actually need the value - perhaps because a
1068 branch circumvented the load - in which case it can discard the value or just
1069 cache it for later use.
1074 ======================= =======================
1076 DIVIDE } Divide instructions generally
1077 DIVIDE } take a long time to perform
1080 Which might appear as this:
1084 --->| B->2 |------>| |
1088 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1089 division speculates on the +-------+ ~ | |
1093 Once the divisions are complete --> : : ~-->| |
1094 the CPU can then perform the : : | |
1095 LOAD with immediate effect : : +-------+
1098 Placing a read barrier or a data dependency barrier just before the second
1102 ======================= =======================
1109 will force any value speculatively obtained to be reconsidered to an extent
1110 dependent on the type of barrier used. If there was no change made to the
1111 speculated memory location, then the speculated value will just be used:
1115 --->| B->2 |------>| |
1119 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1120 division speculates on the +-------+ ~ | |
1125 rrrrrrrrrrrrrrrr~ | |
1132 but if there was an update or an invalidation from another CPU pending, then
1133 the speculation will be cancelled and the value reloaded:
1137 --->| B->2 |------>| |
1141 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1142 division speculates on the +-------+ ~ | |
1147 rrrrrrrrrrrrrrrrr | |
1149 The speculation is discarded ---> --->| A->1 |------>| |
1150 and an updated value is +-------+ | |
1151 retrieved : : +-------+
1157 Transitivity is a deeply intuitive notion about ordering that is not
1158 always provided by real computer systems. The following example
1159 demonstrates transitivity (also called "cumulativity"):
1162 ======================= ======================= =======================
1164 STORE X=1 LOAD X STORE Y=1
1165 <general barrier> <general barrier>
1168 Suppose that CPU 2's load from X returns 1 and its load from Y returns 0.
1169 This indicates that CPU 2's load from X in some sense follows CPU 1's
1170 store to X and that CPU 2's load from Y in some sense preceded CPU 3's
1171 store to Y. The question is then "Can CPU 3's load from X return 0?"
1173 Because CPU 2's load from X in some sense came after CPU 1's store, it
1174 is natural to expect that CPU 3's load from X must therefore return 1.
1175 This expectation is an example of transitivity: if a load executing on
1176 CPU A follows a load from the same variable executing on CPU B, then
1177 CPU A's load must either return the same value that CPU B's load did,
1178 or must return some later value.
1180 In the Linux kernel, use of general memory barriers guarantees
1181 transitivity. Therefore, in the above example, if CPU 2's load from X
1182 returns 1 and its load from Y returns 0, then CPU 3's load from X must
1185 However, transitivity is -not- guaranteed for read or write barriers.
1186 For example, suppose that CPU 2's general barrier in the above example
1187 is changed to a read barrier as shown below:
1190 ======================= ======================= =======================
1192 STORE X=1 LOAD X STORE Y=1
1193 <read barrier> <general barrier>
1196 This substitution destroys transitivity: in this example, it is perfectly
1197 legal for CPU 2's load from X to return 1, its load from Y to return 0,
1198 and CPU 3's load from X to return 0.
1200 The key point is that although CPU 2's read barrier orders its pair
1201 of loads, it does not guarantee to order CPU 1's store. Therefore, if
1202 this example runs on a system where CPUs 1 and 2 share a store buffer
1203 or a level of cache, CPU 2 might have early access to CPU 1's writes.
1204 General barriers are therefore required to ensure that all CPUs agree
1205 on the combined order of CPU 1's and CPU 2's accesses.
1207 To reiterate, if your code requires transitivity, use general barriers
1211 ========================
1212 EXPLICIT KERNEL BARRIERS
1213 ========================
1215 The Linux kernel has a variety of different barriers that act at different
1218 (*) Compiler barrier.
1220 (*) CPU memory barriers.
1222 (*) MMIO write barrier.
1228 The Linux kernel has an explicit compiler barrier function that prevents the
1229 compiler from moving the memory accesses either side of it to the other side:
1233 This is a general barrier -- there are no read-read or write-write variants
1234 of barrier(). However, ACCESS_ONCE() can be thought of as a weak form
1235 for barrier() that affects only the specific accesses flagged by the
1238 The barrier() function has the following effects:
1240 (*) Prevents the compiler from reordering accesses following the
1241 barrier() to precede any accesses preceding the barrier().
1242 One example use for this property is to ease communication between
1243 interrupt-handler code and the code that was interrupted.
1245 (*) Within a loop, forces the compiler to load the variables used
1246 in that loop's conditional on each pass through that loop.
1248 The ACCESS_ONCE() function can prevent any number of optimizations that,
1249 while perfectly safe in single-threaded code, can be fatal in concurrent
1250 code. Here are some examples of these sorts of optimizations:
1252 (*) The compiler is within its rights to merge successive loads from
1253 the same variable. Such merging can cause the compiler to "optimize"
1257 do_something_with(tmp);
1259 into the following code, which, although in some sense legitimate
1260 for single-threaded code, is almost certainly not what the developer
1265 do_something_with(tmp);
1267 Use ACCESS_ONCE() to prevent the compiler from doing this to you:
1269 while (tmp = ACCESS_ONCE(a))
1270 do_something_with(tmp);
1272 (*) The compiler is within its rights to reload a variable, for example,
1273 in cases where high register pressure prevents the compiler from
1274 keeping all data of interest in registers. The compiler might
1275 therefore optimize the variable 'tmp' out of our previous example:
1278 do_something_with(tmp);
1280 This could result in the following code, which is perfectly safe in
1281 single-threaded code, but can be fatal in concurrent code:
1284 do_something_with(a);
1286 For example, the optimized version of this code could result in
1287 passing a zero to do_something_with() in the case where the variable
1288 a was modified by some other CPU between the "while" statement and
1289 the call to do_something_with().
1291 Again, use ACCESS_ONCE() to prevent the compiler from doing this:
1293 while (tmp = ACCESS_ONCE(a))
1294 do_something_with(tmp);
1296 Note that if the compiler runs short of registers, it might save
1297 tmp onto the stack. The overhead of this saving and later restoring
1298 is why compilers reload variables. Doing so is perfectly safe for
1299 single-threaded code, so you need to tell the compiler about cases
1300 where it is not safe.
1302 (*) The compiler is within its rights to omit a load entirely if it knows
1303 what the value will be. For example, if the compiler can prove that
1304 the value of variable 'a' is always zero, it can optimize this code:
1307 do_something_with(tmp);
1313 This transformation is a win for single-threaded code because it gets
1314 rid of a load and a branch. The problem is that the compiler will
1315 carry out its proof assuming that the current CPU is the only one
1316 updating variable 'a'. If variable 'a' is shared, then the compiler's
1317 proof will be erroneous. Use ACCESS_ONCE() to tell the compiler
1318 that it doesn't know as much as it thinks it does:
1320 while (tmp = ACCESS_ONCE(a))
1321 do_something_with(tmp);
1323 But please note that the compiler is also closely watching what you
1324 do with the value after the ACCESS_ONCE(). For example, suppose you
1325 do the following and MAX is a preprocessor macro with the value 1:
1327 while ((tmp = ACCESS_ONCE(a)) % MAX)
1328 do_something_with(tmp);
1330 Then the compiler knows that the result of the "%" operator applied
1331 to MAX will always be zero, again allowing the compiler to optimize
1332 the code into near-nonexistence. (It will still load from the
1335 (*) Similarly, the compiler is within its rights to omit a store entirely
1336 if it knows that the variable already has the value being stored.
1337 Again, the compiler assumes that the current CPU is the only one
1338 storing into the variable, which can cause the compiler to do the
1339 wrong thing for shared variables. For example, suppose you have
1343 /* Code that does not store to variable a. */
1346 The compiler sees that the value of variable 'a' is already zero, so
1347 it might well omit the second store. This would come as a fatal
1348 surprise if some other CPU might have stored to variable 'a' in the
1351 Use ACCESS_ONCE() to prevent the compiler from making this sort of
1355 /* Code that does not store to variable a. */
1358 (*) The compiler is within its rights to reorder memory accesses unless
1359 you tell it not to. For example, consider the following interaction
1360 between process-level code and an interrupt handler:
1362 void process_level(void)
1364 msg = get_message();
1368 void interrupt_handler(void)
1371 process_message(msg);
1374 There is nothing to prevent the the compiler from transforming
1375 process_level() to the following, in fact, this might well be a
1376 win for single-threaded code:
1378 void process_level(void)
1381 msg = get_message();
1384 If the interrupt occurs between these two statement, then
1385 interrupt_handler() might be passed a garbled msg. Use ACCESS_ONCE()
1386 to prevent this as follows:
1388 void process_level(void)
1390 ACCESS_ONCE(msg) = get_message();
1391 ACCESS_ONCE(flag) = true;
1394 void interrupt_handler(void)
1396 if (ACCESS_ONCE(flag))
1397 process_message(ACCESS_ONCE(msg));
1400 Note that the ACCESS_ONCE() wrappers in interrupt_handler()
1401 are needed if this interrupt handler can itself be interrupted
1402 by something that also accesses 'flag' and 'msg', for example,
1403 a nested interrupt or an NMI. Otherwise, ACCESS_ONCE() is not
1404 needed in interrupt_handler() other than for documentation purposes.
1405 (Note also that nested interrupts do not typically occur in modern
1406 Linux kernels, in fact, if an interrupt handler returns with
1407 interrupts enabled, you will get a WARN_ONCE() splat.)
1409 You should assume that the compiler can move ACCESS_ONCE() past
1410 code not containing ACCESS_ONCE(), barrier(), or similar primitives.
1412 This effect could also be achieved using barrier(), but ACCESS_ONCE()
1413 is more selective: With ACCESS_ONCE(), the compiler need only forget
1414 the contents of the indicated memory locations, while with barrier()
1415 the compiler must discard the value of all memory locations that
1416 it has currented cached in any machine registers. Of course,
1417 the compiler must also respect the order in which the ACCESS_ONCE()s
1418 occur, though the CPU of course need not do so.
1420 (*) The compiler is within its rights to invent stores to a variable,
1421 as in the following example:
1428 The compiler might save a branch by optimizing this as follows:
1434 In single-threaded code, this is not only safe, but also saves
1435 a branch. Unfortunately, in concurrent code, this optimization
1436 could cause some other CPU to see a spurious value of 42 -- even
1437 if variable 'a' was never zero -- when loading variable 'b'.
1438 Use ACCESS_ONCE() to prevent this as follows:
1443 ACCESS_ONCE(b) = 42;
1445 The compiler can also invent loads. These are usually less
1446 damaging, but they can result in cache-line bouncing and thus in
1447 poor performance and scalability. Use ACCESS_ONCE() to prevent
1450 (*) For aligned memory locations whose size allows them to be accessed
1451 with a single memory-reference instruction, prevents "load tearing"
1452 and "store tearing," in which a single large access is replaced by
1453 multiple smaller accesses. For example, given an architecture having
1454 16-bit store instructions with 7-bit immediate fields, the compiler
1455 might be tempted to use two 16-bit store-immediate instructions to
1456 implement the following 32-bit store:
1460 Please note that GCC really does use this sort of optimization,
1461 which is not surprising given that it would likely take more
1462 than two instructions to build the constant and then store it.
1463 This optimization can therefore be a win in single-threaded code.
1464 In fact, a recent bug (since fixed) caused GCC to incorrectly use
1465 this optimization in a volatile store. In the absence of such bugs,
1466 use of ACCESS_ONCE() prevents store tearing in the following example:
1468 ACCESS_ONCE(p) = 0x00010002;
1470 Use of packed structures can also result in load and store tearing,
1473 struct __attribute__((__packed__)) foo {
1478 struct foo foo1, foo2;
1485 Because there are no ACCESS_ONCE() wrappers and no volatile markings,
1486 the compiler would be well within its rights to implement these three
1487 assignment statements as a pair of 32-bit loads followed by a pair
1488 of 32-bit stores. This would result in load tearing on 'foo1.b'
1489 and store tearing on 'foo2.b'. ACCESS_ONCE() again prevents tearing
1493 ACCESS_ONCE(foo2.b) = ACCESS_ONCE(foo1.b);
1496 All that aside, it is never necessary to use ACCESS_ONCE() on a variable
1497 that has been marked volatile. For example, because 'jiffies' is marked
1498 volatile, it is never necessary to say ACCESS_ONCE(jiffies). The reason
1499 for this is that ACCESS_ONCE() is implemented as a volatile cast, which
1500 has no effect when its argument is already marked volatile.
1502 Please note that these compiler barriers have no direct effect on the CPU,
1503 which may then reorder things however it wishes.
1509 The Linux kernel has eight basic CPU memory barriers:
1511 TYPE MANDATORY SMP CONDITIONAL
1512 =============== ======================= ===========================
1513 GENERAL mb() smp_mb()
1514 WRITE wmb() smp_wmb()
1515 READ rmb() smp_rmb()
1516 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
1519 All memory barriers except the data dependency barriers imply a compiler
1520 barrier. Data dependencies do not impose any additional compiler ordering.
1522 Aside: In the case of data dependencies, the compiler would be expected to
1523 issue the loads in the correct order (eg. `a[b]` would have to load the value
1524 of b before loading a[b]), however there is no guarantee in the C specification
1525 that the compiler may not speculate the value of b (eg. is equal to 1) and load
1526 a before b (eg. tmp = a[1]; if (b != 1) tmp = a[b]; ). There is also the
1527 problem of a compiler reloading b after having loaded a[b], thus having a newer
1528 copy of b than a[b]. A consensus has not yet been reached about these problems,
1529 however the ACCESS_ONCE macro is a good place to start looking.
1531 SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
1532 systems because it is assumed that a CPU will appear to be self-consistent,
1533 and will order overlapping accesses correctly with respect to itself.
1535 [!] Note that SMP memory barriers _must_ be used to control the ordering of
1536 references to shared memory on SMP systems, though the use of locking instead
1539 Mandatory barriers should not be used to control SMP effects, since mandatory
1540 barriers unnecessarily impose overhead on UP systems. They may, however, be
1541 used to control MMIO effects on accesses through relaxed memory I/O windows.
1542 These are required even on non-SMP systems as they affect the order in which
1543 memory operations appear to a device by prohibiting both the compiler and the
1544 CPU from reordering them.
1547 There are some more advanced barrier functions:
1549 (*) set_mb(var, value)
1551 This assigns the value to the variable and then inserts a full memory
1552 barrier after it, depending on the function. It isn't guaranteed to
1553 insert anything more than a compiler barrier in a UP compilation.
1556 (*) smp_mb__before_atomic_dec();
1557 (*) smp_mb__after_atomic_dec();
1558 (*) smp_mb__before_atomic_inc();
1559 (*) smp_mb__after_atomic_inc();
1561 These are for use with atomic add, subtract, increment and decrement
1562 functions that don't return a value, especially when used for reference
1563 counting. These functions do not imply memory barriers.
1565 As an example, consider a piece of code that marks an object as being dead
1566 and then decrements the object's reference count:
1569 smp_mb__before_atomic_dec();
1570 atomic_dec(&obj->ref_count);
1572 This makes sure that the death mark on the object is perceived to be set
1573 *before* the reference counter is decremented.
1575 See Documentation/atomic_ops.txt for more information. See the "Atomic
1576 operations" subsection for information on where to use these.
1579 (*) smp_mb__before_clear_bit(void);
1580 (*) smp_mb__after_clear_bit(void);
1582 These are for use similar to the atomic inc/dec barriers. These are
1583 typically used for bitwise unlocking operations, so care must be taken as
1584 there are no implicit memory barriers here either.
1586 Consider implementing an unlock operation of some nature by clearing a
1587 locking bit. The clear_bit() would then need to be barriered like this:
1589 smp_mb__before_clear_bit();
1592 This prevents memory operations before the clear leaking to after it. See
1593 the subsection on "Locking Functions" with reference to RELEASE operation
1596 See Documentation/atomic_ops.txt for more information. See the "Atomic
1597 operations" subsection for information on where to use these.
1603 The Linux kernel also has a special barrier for use with memory-mapped I/O
1608 This is a variation on the mandatory write barrier that causes writes to weakly
1609 ordered I/O regions to be partially ordered. Its effects may go beyond the
1610 CPU->Hardware interface and actually affect the hardware at some level.
1612 See the subsection "Locks vs I/O accesses" for more information.
1615 ===============================
1616 IMPLICIT KERNEL MEMORY BARRIERS
1617 ===============================
1619 Some of the other functions in the linux kernel imply memory barriers, amongst
1620 which are locking and scheduling functions.
1622 This specification is a _minimum_ guarantee; any particular architecture may
1623 provide more substantial guarantees, but these may not be relied upon outside
1624 of arch specific code.
1630 The Linux kernel has a number of locking constructs:
1639 In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
1640 for each construct. These operations all imply certain barriers:
1642 (1) ACQUIRE operation implication:
1644 Memory operations issued after the ACQUIRE will be completed after the
1645 ACQUIRE operation has completed.
1647 Memory operations issued before the ACQUIRE may be completed after the
1648 ACQUIRE operation has completed. An smp_mb__before_spinlock(), combined
1649 with a following ACQUIRE, orders prior loads against subsequent stores and
1650 stores and prior stores against subsequent stores. Note that this is
1651 weaker than smp_mb()! The smp_mb__before_spinlock() primitive is free on
1654 (2) RELEASE operation implication:
1656 Memory operations issued before the RELEASE will be completed before the
1657 RELEASE operation has completed.
1659 Memory operations issued after the RELEASE may be completed before the
1660 RELEASE operation has completed.
1662 (3) ACQUIRE vs ACQUIRE implication:
1664 All ACQUIRE operations issued before another ACQUIRE operation will be
1665 completed before that ACQUIRE operation.
1667 (4) ACQUIRE vs RELEASE implication:
1669 All ACQUIRE operations issued before a RELEASE operation will be
1670 completed before the RELEASE operation.
1672 (5) Failed conditional ACQUIRE implication:
1674 Certain locking variants of the ACQUIRE operation may fail, either due to
1675 being unable to get the lock immediately, or due to receiving an unblocked
1676 signal whilst asleep waiting for the lock to become available. Failed
1677 locks do not imply any sort of barrier.
1679 [!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only
1680 one-way barriers is that the effects of instructions outside of a critical
1681 section may seep into the inside of the critical section.
1683 An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
1684 because it is possible for an access preceding the ACQUIRE to happen after the
1685 ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
1686 the two accesses can themselves then cross:
1695 ACQUIRE M, STORE *B, STORE *A, RELEASE M
1697 This same reordering can of course occur if the lock's ACQUIRE and RELEASE are
1698 to the same lock variable, but only from the perspective of another CPU not
1701 In short, a RELEASE followed by an ACQUIRE may -not- be assumed to be a full
1702 memory barrier because it is possible for a preceding RELEASE to pass a
1703 later ACQUIRE from the viewpoint of the CPU, but not from the viewpoint
1704 of the compiler. Note that deadlocks cannot be introduced by this
1705 interchange because if such a deadlock threatened, the RELEASE would
1708 If it is necessary for a RELEASE-ACQUIRE pair to produce a full barrier, the
1709 ACQUIRE can be followed by an smp_mb__after_unlock_lock() invocation. This
1710 will produce a full barrier if either (a) the RELEASE and the ACQUIRE are
1711 executed by the same CPU or task, or (b) the RELEASE and ACQUIRE act on the
1712 same variable. The smp_mb__after_unlock_lock() primitive is free on many
1713 architectures. Without smp_mb__after_unlock_lock(), the critical sections
1714 corresponding to the RELEASE and the ACQUIRE can cross:
1723 ACQUIRE N, STORE *B, STORE *A, RELEASE M
1725 With smp_mb__after_unlock_lock(), they cannot, so that:
1730 smp_mb__after_unlock_lock();
1733 will always occur as either of the following:
1735 STORE *A, RELEASE, ACQUIRE, STORE *B
1736 STORE *A, ACQUIRE, RELEASE, STORE *B
1738 If the RELEASE and ACQUIRE were instead both operating on the same lock
1739 variable, only the first of these two alternatives can occur.
1741 Locks and semaphores may not provide any guarantee of ordering on UP compiled
1742 systems, and so cannot be counted on in such a situation to actually achieve
1743 anything at all - especially with respect to I/O accesses - unless combined
1744 with interrupt disabling operations.
1746 See also the section on "Inter-CPU locking barrier effects".
1749 As an example, consider the following:
1760 The following sequence of events is acceptable:
1762 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
1764 [+] Note that {*F,*A} indicates a combined access.
1766 But none of the following are:
1768 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
1769 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
1770 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
1771 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
1775 INTERRUPT DISABLING FUNCTIONS
1776 -----------------------------
1778 Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts
1779 (RELEASE equivalent) will act as compiler barriers only. So if memory or I/O
1780 barriers are required in such a situation, they must be provided from some
1784 SLEEP AND WAKE-UP FUNCTIONS
1785 ---------------------------
1787 Sleeping and waking on an event flagged in global data can be viewed as an
1788 interaction between two pieces of data: the task state of the task waiting for
1789 the event and the global data used to indicate the event. To make sure that
1790 these appear to happen in the right order, the primitives to begin the process
1791 of going to sleep, and the primitives to initiate a wake up imply certain
1794 Firstly, the sleeper normally follows something like this sequence of events:
1797 set_current_state(TASK_UNINTERRUPTIBLE);
1798 if (event_indicated)
1803 A general memory barrier is interpolated automatically by set_current_state()
1804 after it has altered the task state:
1807 ===============================
1808 set_current_state();
1810 STORE current->state
1812 LOAD event_indicated
1814 set_current_state() may be wrapped by:
1817 prepare_to_wait_exclusive();
1819 which therefore also imply a general memory barrier after setting the state.
1820 The whole sequence above is available in various canned forms, all of which
1821 interpolate the memory barrier in the right place:
1824 wait_event_interruptible();
1825 wait_event_interruptible_exclusive();
1826 wait_event_interruptible_timeout();
1827 wait_event_killable();
1828 wait_event_timeout();
1833 Secondly, code that performs a wake up normally follows something like this:
1835 event_indicated = 1;
1836 wake_up(&event_wait_queue);
1840 event_indicated = 1;
1841 wake_up_process(event_daemon);
1843 A write memory barrier is implied by wake_up() and co. if and only if they wake
1844 something up. The barrier occurs before the task state is cleared, and so sits
1845 between the STORE to indicate the event and the STORE to set TASK_RUNNING:
1848 =============================== ===============================
1849 set_current_state(); STORE event_indicated
1850 set_mb(); wake_up();
1851 STORE current->state <write barrier>
1852 <general barrier> STORE current->state
1853 LOAD event_indicated
1855 The available waker functions include:
1861 wake_up_interruptible();
1862 wake_up_interruptible_all();
1863 wake_up_interruptible_nr();
1864 wake_up_interruptible_poll();
1865 wake_up_interruptible_sync();
1866 wake_up_interruptible_sync_poll();
1868 wake_up_locked_poll();
1874 [!] Note that the memory barriers implied by the sleeper and the waker do _not_
1875 order multiple stores before the wake-up with respect to loads of those stored
1876 values after the sleeper has called set_current_state(). For instance, if the
1879 set_current_state(TASK_INTERRUPTIBLE);
1880 if (event_indicated)
1882 __set_current_state(TASK_RUNNING);
1883 do_something(my_data);
1888 event_indicated = 1;
1889 wake_up(&event_wait_queue);
1891 there's no guarantee that the change to event_indicated will be perceived by
1892 the sleeper as coming after the change to my_data. In such a circumstance, the
1893 code on both sides must interpolate its own memory barriers between the
1894 separate data accesses. Thus the above sleeper ought to do:
1896 set_current_state(TASK_INTERRUPTIBLE);
1897 if (event_indicated) {
1899 do_something(my_data);
1902 and the waker should do:
1906 event_indicated = 1;
1907 wake_up(&event_wait_queue);
1910 MISCELLANEOUS FUNCTIONS
1911 -----------------------
1913 Other functions that imply barriers:
1915 (*) schedule() and similar imply full memory barriers.
1918 ===================================
1919 INTER-CPU ACQUIRING BARRIER EFFECTS
1920 ===================================
1922 On SMP systems locking primitives give a more substantial form of barrier: one
1923 that does affect memory access ordering on other CPUs, within the context of
1924 conflict on any particular lock.
1927 ACQUIRES VS MEMORY ACCESSES
1928 ---------------------------
1930 Consider the following: the system has a pair of spinlocks (M) and (Q), and
1931 three CPUs; then should the following sequence of events occur:
1934 =============================== ===============================
1935 ACCESS_ONCE(*A) = a; ACCESS_ONCE(*E) = e;
1937 ACCESS_ONCE(*B) = b; ACCESS_ONCE(*F) = f;
1938 ACCESS_ONCE(*C) = c; ACCESS_ONCE(*G) = g;
1940 ACCESS_ONCE(*D) = d; ACCESS_ONCE(*H) = h;
1942 Then there is no guarantee as to what order CPU 3 will see the accesses to *A
1943 through *H occur in, other than the constraints imposed by the separate locks
1944 on the separate CPUs. It might, for example, see:
1946 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
1948 But it won't see any of:
1950 *B, *C or *D preceding ACQUIRE M
1951 *A, *B or *C following RELEASE M
1952 *F, *G or *H preceding ACQUIRE Q
1953 *E, *F or *G following RELEASE Q
1956 However, if the following occurs:
1959 =============================== ===============================
1960 ACCESS_ONCE(*A) = a;
1962 ACCESS_ONCE(*B) = b;
1963 ACCESS_ONCE(*C) = c;
1965 ACCESS_ONCE(*D) = d; ACCESS_ONCE(*E) = e;
1967 smp_mb__after_unlock_lock();
1968 ACCESS_ONCE(*F) = f;
1969 ACCESS_ONCE(*G) = g;
1971 ACCESS_ONCE(*H) = h;
1975 *E, ACQUIRE M [1], *C, *B, *A, RELEASE M [1],
1976 ACQUIRE M [2], *H, *F, *G, RELEASE M [2], *D
1978 But assuming CPU 1 gets the lock first, CPU 3 won't see any of:
1980 *B, *C, *D, *F, *G or *H preceding ACQUIRE M [1]
1981 *A, *B or *C following RELEASE M [1]
1982 *F, *G or *H preceding ACQUIRE M [2]
1983 *A, *B, *C, *E, *F or *G following RELEASE M [2]
1985 Note that the smp_mb__after_unlock_lock() is critically important
1986 here: Without it CPU 3 might see some of the above orderings.
1987 Without smp_mb__after_unlock_lock(), the accesses are not guaranteed
1988 to be seen in order unless CPU 3 holds lock M.
1991 ACQUIRES VS I/O ACCESSES
1992 ------------------------
1994 Under certain circumstances (especially involving NUMA), I/O accesses within
1995 two spinlocked sections on two different CPUs may be seen as interleaved by the
1996 PCI bridge, because the PCI bridge does not necessarily participate in the
1997 cache-coherence protocol, and is therefore incapable of issuing the required
1998 read memory barriers.
2003 =============================== ===============================
2013 may be seen by the PCI bridge as follows:
2015 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
2017 which would probably cause the hardware to malfunction.
2020 What is necessary here is to intervene with an mmiowb() before dropping the
2021 spinlock, for example:
2024 =============================== ===============================
2036 this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
2037 before either of the stores issued on CPU 2.
2040 Furthermore, following a store by a load from the same device obviates the need
2041 for the mmiowb(), because the load forces the store to complete before the load
2045 =============================== ===============================
2056 See Documentation/DocBook/deviceiobook.tmpl for more information.
2059 =================================
2060 WHERE ARE MEMORY BARRIERS NEEDED?
2061 =================================
2063 Under normal operation, memory operation reordering is generally not going to
2064 be a problem as a single-threaded linear piece of code will still appear to
2065 work correctly, even if it's in an SMP kernel. There are, however, four
2066 circumstances in which reordering definitely _could_ be a problem:
2068 (*) Interprocessor interaction.
2070 (*) Atomic operations.
2072 (*) Accessing devices.
2077 INTERPROCESSOR INTERACTION
2078 --------------------------
2080 When there's a system with more than one processor, more than one CPU in the
2081 system may be working on the same data set at the same time. This can cause
2082 synchronisation problems, and the usual way of dealing with them is to use
2083 locks. Locks, however, are quite expensive, and so it may be preferable to
2084 operate without the use of a lock if at all possible. In such a case
2085 operations that affect both CPUs may have to be carefully ordered to prevent
2088 Consider, for example, the R/W semaphore slow path. Here a waiting process is
2089 queued on the semaphore, by virtue of it having a piece of its stack linked to
2090 the semaphore's list of waiting processes:
2092 struct rw_semaphore {
2095 struct list_head waiters;
2098 struct rwsem_waiter {
2099 struct list_head list;
2100 struct task_struct *task;
2103 To wake up a particular waiter, the up_read() or up_write() functions have to:
2105 (1) read the next pointer from this waiter's record to know as to where the
2106 next waiter record is;
2108 (2) read the pointer to the waiter's task structure;
2110 (3) clear the task pointer to tell the waiter it has been given the semaphore;
2112 (4) call wake_up_process() on the task; and
2114 (5) release the reference held on the waiter's task struct.
2116 In other words, it has to perform this sequence of events:
2118 LOAD waiter->list.next;
2124 and if any of these steps occur out of order, then the whole thing may
2127 Once it has queued itself and dropped the semaphore lock, the waiter does not
2128 get the lock again; it instead just waits for its task pointer to be cleared
2129 before proceeding. Since the record is on the waiter's stack, this means that
2130 if the task pointer is cleared _before_ the next pointer in the list is read,
2131 another CPU might start processing the waiter and might clobber the waiter's
2132 stack before the up*() function has a chance to read the next pointer.
2134 Consider then what might happen to the above sequence of events:
2137 =============================== ===============================
2144 Woken up by other event
2149 foo() clobbers *waiter
2151 LOAD waiter->list.next;
2154 This could be dealt with using the semaphore lock, but then the down_xxx()
2155 function has to needlessly get the spinlock again after being woken up.
2157 The way to deal with this is to insert a general SMP memory barrier:
2159 LOAD waiter->list.next;
2166 In this case, the barrier makes a guarantee that all memory accesses before the
2167 barrier will appear to happen before all the memory accesses after the barrier
2168 with respect to the other CPUs on the system. It does _not_ guarantee that all
2169 the memory accesses before the barrier will be complete by the time the barrier
2170 instruction itself is complete.
2172 On a UP system - where this wouldn't be a problem - the smp_mb() is just a
2173 compiler barrier, thus making sure the compiler emits the instructions in the
2174 right order without actually intervening in the CPU. Since there's only one
2175 CPU, that CPU's dependency ordering logic will take care of everything else.
2181 Whilst they are technically interprocessor interaction considerations, atomic
2182 operations are noted specially as some of them imply full memory barriers and
2183 some don't, but they're very heavily relied on as a group throughout the
2186 Any atomic operation that modifies some state in memory and returns information
2187 about the state (old or new) implies an SMP-conditional general memory barrier
2188 (smp_mb()) on each side of the actual operation (with the exception of
2189 explicit lock operations, described later). These include:
2193 atomic_xchg(); atomic_long_xchg();
2194 atomic_cmpxchg(); atomic_long_cmpxchg();
2195 atomic_inc_return(); atomic_long_inc_return();
2196 atomic_dec_return(); atomic_long_dec_return();
2197 atomic_add_return(); atomic_long_add_return();
2198 atomic_sub_return(); atomic_long_sub_return();
2199 atomic_inc_and_test(); atomic_long_inc_and_test();
2200 atomic_dec_and_test(); atomic_long_dec_and_test();
2201 atomic_sub_and_test(); atomic_long_sub_and_test();
2202 atomic_add_negative(); atomic_long_add_negative();
2204 test_and_clear_bit();
2205 test_and_change_bit();
2207 /* when succeeds (returns 1) */
2208 atomic_add_unless(); atomic_long_add_unless();
2210 These are used for such things as implementing ACQUIRE-class and RELEASE-class
2211 operations and adjusting reference counters towards object destruction, and as
2212 such the implicit memory barrier effects are necessary.
2215 The following operations are potential problems as they do _not_ imply memory
2216 barriers, but might be used for implementing such things as RELEASE-class
2224 With these the appropriate explicit memory barrier should be used if necessary
2225 (smp_mb__before_clear_bit() for instance).
2228 The following also do _not_ imply memory barriers, and so may require explicit
2229 memory barriers under some circumstances (smp_mb__before_atomic_dec() for
2237 If they're used for statistics generation, then they probably don't need memory
2238 barriers, unless there's a coupling between statistical data.
2240 If they're used for reference counting on an object to control its lifetime,
2241 they probably don't need memory barriers because either the reference count
2242 will be adjusted inside a locked section, or the caller will already hold
2243 sufficient references to make the lock, and thus a memory barrier unnecessary.
2245 If they're used for constructing a lock of some description, then they probably
2246 do need memory barriers as a lock primitive generally has to do things in a
2249 Basically, each usage case has to be carefully considered as to whether memory
2250 barriers are needed or not.
2252 The following operations are special locking primitives:
2254 test_and_set_bit_lock();
2256 __clear_bit_unlock();
2258 These implement ACQUIRE-class and RELEASE-class operations. These should be used in
2259 preference to other operations when implementing locking primitives, because
2260 their implementations can be optimised on many architectures.
2262 [!] Note that special memory barrier primitives are available for these
2263 situations because on some CPUs the atomic instructions used imply full memory
2264 barriers, and so barrier instructions are superfluous in conjunction with them,
2265 and in such cases the special barrier primitives will be no-ops.
2267 See Documentation/atomic_ops.txt for more information.
2273 Many devices can be memory mapped, and so appear to the CPU as if they're just
2274 a set of memory locations. To control such a device, the driver usually has to
2275 make the right memory accesses in exactly the right order.
2277 However, having a clever CPU or a clever compiler creates a potential problem
2278 in that the carefully sequenced accesses in the driver code won't reach the
2279 device in the requisite order if the CPU or the compiler thinks it is more
2280 efficient to reorder, combine or merge accesses - something that would cause
2281 the device to malfunction.
2283 Inside of the Linux kernel, I/O should be done through the appropriate accessor
2284 routines - such as inb() or writel() - which know how to make such accesses
2285 appropriately sequential. Whilst this, for the most part, renders the explicit
2286 use of memory barriers unnecessary, there are a couple of situations where they
2289 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
2290 so for _all_ general drivers locks should be used and mmiowb() must be
2291 issued prior to unlocking the critical section.
2293 (2) If the accessor functions are used to refer to an I/O memory window with
2294 relaxed memory access properties, then _mandatory_ memory barriers are
2295 required to enforce ordering.
2297 See Documentation/DocBook/deviceiobook.tmpl for more information.
2303 A driver may be interrupted by its own interrupt service routine, and thus the
2304 two parts of the driver may interfere with each other's attempts to control or
2307 This may be alleviated - at least in part - by disabling local interrupts (a
2308 form of locking), such that the critical operations are all contained within
2309 the interrupt-disabled section in the driver. Whilst the driver's interrupt
2310 routine is executing, the driver's core may not run on the same CPU, and its
2311 interrupt is not permitted to happen again until the current interrupt has been
2312 handled, thus the interrupt handler does not need to lock against that.
2314 However, consider a driver that was talking to an ethernet card that sports an
2315 address register and a data register. If that driver's core talks to the card
2316 under interrupt-disablement and then the driver's interrupt handler is invoked:
2327 The store to the data register might happen after the second store to the
2328 address register if ordering rules are sufficiently relaxed:
2330 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
2333 If ordering rules are relaxed, it must be assumed that accesses done inside an
2334 interrupt disabled section may leak outside of it and may interleave with
2335 accesses performed in an interrupt - and vice versa - unless implicit or
2336 explicit barriers are used.
2338 Normally this won't be a problem because the I/O accesses done inside such
2339 sections will include synchronous load operations on strictly ordered I/O
2340 registers that form implicit I/O barriers. If this isn't sufficient then an
2341 mmiowb() may need to be used explicitly.
2344 A similar situation may occur between an interrupt routine and two routines
2345 running on separate CPUs that communicate with each other. If such a case is
2346 likely, then interrupt-disabling locks should be used to guarantee ordering.
2349 ==========================
2350 KERNEL I/O BARRIER EFFECTS
2351 ==========================
2353 When accessing I/O memory, drivers should use the appropriate accessor
2358 These are intended to talk to I/O space rather than memory space, but
2359 that's primarily a CPU-specific concept. The i386 and x86_64 processors do
2360 indeed have special I/O space access cycles and instructions, but many
2361 CPUs don't have such a concept.
2363 The PCI bus, amongst others, defines an I/O space concept which - on such
2364 CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
2365 space. However, it may also be mapped as a virtual I/O space in the CPU's
2366 memory map, particularly on those CPUs that don't support alternate I/O
2369 Accesses to this space may be fully synchronous (as on i386), but
2370 intermediary bridges (such as the PCI host bridge) may not fully honour
2373 They are guaranteed to be fully ordered with respect to each other.
2375 They are not guaranteed to be fully ordered with respect to other types of
2376 memory and I/O operation.
2378 (*) readX(), writeX():
2380 Whether these are guaranteed to be fully ordered and uncombined with
2381 respect to each other on the issuing CPU depends on the characteristics
2382 defined for the memory window through which they're accessing. On later
2383 i386 architecture machines, for example, this is controlled by way of the
2386 Ordinarily, these will be guaranteed to be fully ordered and uncombined,
2387 provided they're not accessing a prefetchable device.
2389 However, intermediary hardware (such as a PCI bridge) may indulge in
2390 deferral if it so wishes; to flush a store, a load from the same location
2391 is preferred[*], but a load from the same device or from configuration
2392 space should suffice for PCI.
2394 [*] NOTE! attempting to load from the same location as was written to may
2395 cause a malfunction - consider the 16550 Rx/Tx serial registers for
2398 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
2399 force stores to be ordered.
2401 Please refer to the PCI specification for more information on interactions
2402 between PCI transactions.
2406 These are similar to readX(), but are not guaranteed to be ordered in any
2407 way. Be aware that there is no I/O read barrier available.
2409 (*) ioreadX(), iowriteX()
2411 These will perform appropriately for the type of access they're actually
2412 doing, be it inX()/outX() or readX()/writeX().
2415 ========================================
2416 ASSUMED MINIMUM EXECUTION ORDERING MODEL
2417 ========================================
2419 It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2420 maintain the appearance of program causality with respect to itself. Some CPUs
2421 (such as i386 or x86_64) are more constrained than others (such as powerpc or
2422 frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
2423 of arch-specific code.
2425 This means that it must be considered that the CPU will execute its instruction
2426 stream in any order it feels like - or even in parallel - provided that if an
2427 instruction in the stream depends on an earlier instruction, then that
2428 earlier instruction must be sufficiently complete[*] before the later
2429 instruction may proceed; in other words: provided that the appearance of
2430 causality is maintained.
2432 [*] Some instructions have more than one effect - such as changing the
2433 condition codes, changing registers or changing memory - and different
2434 instructions may depend on different effects.
2436 A CPU may also discard any instruction sequence that winds up having no
2437 ultimate effect. For example, if two adjacent instructions both load an
2438 immediate value into the same register, the first may be discarded.
2441 Similarly, it has to be assumed that compiler might reorder the instruction
2442 stream in any way it sees fit, again provided the appearance of causality is
2446 ============================
2447 THE EFFECTS OF THE CPU CACHE
2448 ============================
2450 The way cached memory operations are perceived across the system is affected to
2451 a certain extent by the caches that lie between CPUs and memory, and by the
2452 memory coherence system that maintains the consistency of state in the system.
2454 As far as the way a CPU interacts with another part of the system through the
2455 caches goes, the memory system has to include the CPU's caches, and memory
2456 barriers for the most part act at the interface between the CPU and its cache
2457 (memory barriers logically act on the dotted line in the following diagram):
2459 <--- CPU ---> : <----------- Memory ----------->
2461 +--------+ +--------+ : +--------+ +-----------+
2462 | | | | : | | | | +--------+
2463 | CPU | | Memory | : | CPU | | | | |
2464 | Core |--->| Access |----->| Cache |<-->| | | |
2465 | | | Queue | : | | | |--->| Memory |
2466 | | | | : | | | | | |
2467 +--------+ +--------+ : +--------+ | | | |
2468 : | Cache | +--------+
2470 : | Mechanism | +--------+
2471 +--------+ +--------+ : +--------+ | | | |
2472 | | | | : | | | | | |
2473 | CPU | | Memory | : | CPU | | |--->| Device |
2474 | Core |--->| Access |----->| Cache |<-->| | | |
2475 | | | Queue | : | | | | | |
2476 | | | | : | | | | +--------+
2477 +--------+ +--------+ : +--------+ +-----------+
2481 Although any particular load or store may not actually appear outside of the
2482 CPU that issued it since it may have been satisfied within the CPU's own cache,
2483 it will still appear as if the full memory access had taken place as far as the
2484 other CPUs are concerned since the cache coherency mechanisms will migrate the
2485 cacheline over to the accessing CPU and propagate the effects upon conflict.
2487 The CPU core may execute instructions in any order it deems fit, provided the
2488 expected program causality appears to be maintained. Some of the instructions
2489 generate load and store operations which then go into the queue of memory
2490 accesses to be performed. The core may place these in the queue in any order
2491 it wishes, and continue execution until it is forced to wait for an instruction
2494 What memory barriers are concerned with is controlling the order in which
2495 accesses cross from the CPU side of things to the memory side of things, and
2496 the order in which the effects are perceived to happen by the other observers
2499 [!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2500 their own loads and stores as if they had happened in program order.
2502 [!] MMIO or other device accesses may bypass the cache system. This depends on
2503 the properties of the memory window through which devices are accessed and/or
2504 the use of any special device communication instructions the CPU may have.
2510 Life isn't quite as simple as it may appear above, however: for while the
2511 caches are expected to be coherent, there's no guarantee that that coherency
2512 will be ordered. This means that whilst changes made on one CPU will
2513 eventually become visible on all CPUs, there's no guarantee that they will
2514 become apparent in the same order on those other CPUs.
2517 Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
2518 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2523 +--------+ : +--->| Cache A |<------->| |
2524 | | : | +---------+ | |
2526 | | : | +---------+ | |
2527 +--------+ : +--->| Cache B |<------->| |
2530 : +---------+ | System |
2531 +--------+ : +--->| Cache C |<------->| |
2532 | | : | +---------+ | |
2534 | | : | +---------+ | |
2535 +--------+ : +--->| Cache D |<------->| |
2540 Imagine the system has the following properties:
2542 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
2545 (*) an even-numbered cache line may be in cache B, cache D or it may still be
2548 (*) whilst the CPU core is interrogating one cache, the other cache may be
2549 making use of the bus to access the rest of the system - perhaps to
2550 displace a dirty cacheline or to do a speculative load;
2552 (*) each cache has a queue of operations that need to be applied to that cache
2553 to maintain coherency with the rest of the system;
2555 (*) the coherency queue is not flushed by normal loads to lines already
2556 present in the cache, even though the contents of the queue may
2557 potentially affect those loads.
2559 Imagine, then, that two writes are made on the first CPU, with a write barrier
2560 between them to guarantee that they will appear to reach that CPU's caches in
2561 the requisite order:
2564 =============== =============== =======================================
2565 u == 0, v == 1 and p == &u, q == &u
2567 smp_wmb(); Make sure change to v is visible before
2569 <A:modify v=2> v is now in cache A exclusively
2571 <B:modify p=&v> p is now in cache B exclusively
2573 The write memory barrier forces the other CPUs in the system to perceive that
2574 the local CPU's caches have apparently been updated in the correct order. But
2575 now imagine that the second CPU wants to read those values:
2578 =============== =============== =======================================
2583 The above pair of reads may then fail to happen in the expected order, as the
2584 cacheline holding p may get updated in one of the second CPU's caches whilst
2585 the update to the cacheline holding v is delayed in the other of the second
2586 CPU's caches by some other cache event:
2589 =============== =============== =======================================
2590 u == 0, v == 1 and p == &u, q == &u
2593 <A:modify v=2> <C:busy>
2597 <B:modify p=&v> <D:commit p=&v>
2600 <C:read *q> Reads from v before v updated in cache
2604 Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
2605 no guarantee that, without intervention, the order of update will be the same
2606 as that committed on CPU 1.
2609 To intervene, we need to interpolate a data dependency barrier or a read
2610 barrier between the loads. This will force the cache to commit its coherency
2611 queue before processing any further requests:
2614 =============== =============== =======================================
2615 u == 0, v == 1 and p == &u, q == &u
2618 <A:modify v=2> <C:busy>
2622 <B:modify p=&v> <D:commit p=&v>
2624 smp_read_barrier_depends()
2628 <C:read *q> Reads from v after v updated in cache
2631 This sort of problem can be encountered on DEC Alpha processors as they have a
2632 split cache that improves performance by making better use of the data bus.
2633 Whilst most CPUs do imply a data dependency barrier on the read when a memory
2634 access depends on a read, not all do, so it may not be relied on.
2636 Other CPUs may also have split caches, but must coordinate between the various
2637 cachelets for normal memory accesses. The semantics of the Alpha removes the
2638 need for coordination in the absence of memory barriers.
2641 CACHE COHERENCY VS DMA
2642 ----------------------
2644 Not all systems maintain cache coherency with respect to devices doing DMA. In
2645 such cases, a device attempting DMA may obtain stale data from RAM because
2646 dirty cache lines may be resident in the caches of various CPUs, and may not
2647 have been written back to RAM yet. To deal with this, the appropriate part of
2648 the kernel must flush the overlapping bits of cache on each CPU (and maybe
2649 invalidate them as well).
2651 In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2652 cache lines being written back to RAM from a CPU's cache after the device has
2653 installed its own data, or cache lines present in the CPU's cache may simply
2654 obscure the fact that RAM has been updated, until at such time as the cacheline
2655 is discarded from the CPU's cache and reloaded. To deal with this, the
2656 appropriate part of the kernel must invalidate the overlapping bits of the
2659 See Documentation/cachetlb.txt for more information on cache management.
2662 CACHE COHERENCY VS MMIO
2663 -----------------------
2665 Memory mapped I/O usually takes place through memory locations that are part of
2666 a window in the CPU's memory space that has different properties assigned than
2667 the usual RAM directed window.
2669 Amongst these properties is usually the fact that such accesses bypass the
2670 caching entirely and go directly to the device buses. This means MMIO accesses
2671 may, in effect, overtake accesses to cached memory that were emitted earlier.
2672 A memory barrier isn't sufficient in such a case, but rather the cache must be
2673 flushed between the cached memory write and the MMIO access if the two are in
2677 =========================
2678 THE THINGS CPUS GET UP TO
2679 =========================
2681 A programmer might take it for granted that the CPU will perform memory
2682 operations in exactly the order specified, so that if the CPU is, for example,
2683 given the following piece of code to execute:
2685 a = ACCESS_ONCE(*A);
2686 ACCESS_ONCE(*B) = b;
2687 c = ACCESS_ONCE(*C);
2688 d = ACCESS_ONCE(*D);
2689 ACCESS_ONCE(*E) = e;
2691 they would then expect that the CPU will complete the memory operation for each
2692 instruction before moving on to the next one, leading to a definite sequence of
2693 operations as seen by external observers in the system:
2695 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2698 Reality is, of course, much messier. With many CPUs and compilers, the above
2699 assumption doesn't hold because:
2701 (*) loads are more likely to need to be completed immediately to permit
2702 execution progress, whereas stores can often be deferred without a
2705 (*) loads may be done speculatively, and the result discarded should it prove
2706 to have been unnecessary;
2708 (*) loads may be done speculatively, leading to the result having been fetched
2709 at the wrong time in the expected sequence of events;
2711 (*) the order of the memory accesses may be rearranged to promote better use
2712 of the CPU buses and caches;
2714 (*) loads and stores may be combined to improve performance when talking to
2715 memory or I/O hardware that can do batched accesses of adjacent locations,
2716 thus cutting down on transaction setup costs (memory and PCI devices may
2717 both be able to do this); and
2719 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2720 mechanisms may alleviate this - once the store has actually hit the cache
2721 - there's no guarantee that the coherency management will be propagated in
2722 order to other CPUs.
2724 So what another CPU, say, might actually observe from the above piece of code
2727 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2729 (Where "LOAD {*C,*D}" is a combined load)
2732 However, it is guaranteed that a CPU will be self-consistent: it will see its
2733 _own_ accesses appear to be correctly ordered, without the need for a memory
2734 barrier. For instance with the following code:
2736 U = ACCESS_ONCE(*A);
2737 ACCESS_ONCE(*A) = V;
2738 ACCESS_ONCE(*A) = W;
2739 X = ACCESS_ONCE(*A);
2740 ACCESS_ONCE(*A) = Y;
2741 Z = ACCESS_ONCE(*A);
2743 and assuming no intervention by an external influence, it can be assumed that
2744 the final result will appear to be:
2746 U == the original value of *A
2751 The code above may cause the CPU to generate the full sequence of memory
2754 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2756 in that order, but, without intervention, the sequence may have almost any
2757 combination of elements combined or discarded, provided the program's view of
2758 the world remains consistent. Note that ACCESS_ONCE() is -not- optional
2759 in the above example, as there are architectures where a given CPU might
2760 interchange successive loads to the same location. On such architectures,
2761 ACCESS_ONCE() does whatever is necessary to prevent this, for example, on
2762 Itanium the volatile casts used by ACCESS_ONCE() cause GCC to emit the
2763 special ld.acq and st.rel instructions that prevent such reordering.
2765 The compiler may also combine, discard or defer elements of the sequence before
2766 the CPU even sees them.
2777 since, without either a write barrier or an ACCESS_ONCE(), it can be
2778 assumed that the effect of the storage of V to *A is lost. Similarly:
2783 may, without a memory barrier or an ACCESS_ONCE(), be reduced to:
2788 and the LOAD operation never appear outside of the CPU.
2791 AND THEN THERE'S THE ALPHA
2792 --------------------------
2794 The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
2795 some versions of the Alpha CPU have a split data cache, permitting them to have
2796 two semantically-related cache lines updated at separate times. This is where
2797 the data dependency barrier really becomes necessary as this synchronises both
2798 caches with the memory coherence system, thus making it seem like pointer
2799 changes vs new data occur in the right order.
2801 The Alpha defines the Linux kernel's memory barrier model.
2803 See the subsection on "Cache Coherency" above.
2813 Memory barriers can be used to implement circular buffering without the need
2814 of a lock to serialise the producer with the consumer. See:
2816 Documentation/circular-buffers.txt
2825 Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
2827 Chapter 5.2: Physical Address Space Characteristics
2828 Chapter 5.4: Caches and Write Buffers
2829 Chapter 5.5: Data Sharing
2830 Chapter 5.6: Read/Write Ordering
2832 AMD64 Architecture Programmer's Manual Volume 2: System Programming
2833 Chapter 7.1: Memory-Access Ordering
2834 Chapter 7.4: Buffering and Combining Memory Writes
2836 IA-32 Intel Architecture Software Developer's Manual, Volume 3:
2837 System Programming Guide
2838 Chapter 7.1: Locked Atomic Operations
2839 Chapter 7.2: Memory Ordering
2840 Chapter 7.4: Serializing Instructions
2842 The SPARC Architecture Manual, Version 9
2843 Chapter 8: Memory Models
2844 Appendix D: Formal Specification of the Memory Models
2845 Appendix J: Programming with the Memory Models
2847 UltraSPARC Programmer Reference Manual
2848 Chapter 5: Memory Accesses and Cacheability
2849 Chapter 15: Sparc-V9 Memory Models
2851 UltraSPARC III Cu User's Manual
2852 Chapter 9: Memory Models
2854 UltraSPARC IIIi Processor User's Manual
2855 Chapter 8: Memory Models
2857 UltraSPARC Architecture 2005
2859 Appendix D: Formal Specifications of the Memory Models
2861 UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
2862 Chapter 8: Memory Models
2863 Appendix F: Caches and Cache Coherency
2865 Solaris Internals, Core Kernel Architecture, p63-68:
2866 Chapter 3.3: Hardware Considerations for Locks and
2869 Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
2870 for Kernel Programmers:
2871 Chapter 13: Other Memory Models
2873 Intel Itanium Architecture Software Developer's Manual: Volume 1:
2874 Section 2.6: Speculation
2875 Section 4.4: Memory Access
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