5 This document is an overview of the basic I2C transactions and the kernel
11 =============== =============================================================
14 Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0.
15 A, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit
16 Addr (7 bits) I2C 7 bit address. Note that this can be expanded to
17 get a 10 bit I2C address.
18 Data (8 bits) A plain data byte.
20 [..] Data sent by I2C device, as opposed to data sent by the
22 =============== =============================================================
25 Simple send transaction
26 =======================
28 Implemented by i2c_master_send()::
30 S Addr Wr [A] Data [A] Data [A] ... [A] Data [A] P
33 Simple receive transaction
34 ==========================
36 Implemented by i2c_master_recv()::
38 S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
44 Implemented by i2c_transfer().
46 They are just like the above transactions, but instead of a stop
47 condition P a start condition S is sent and the transaction continues.
48 An example of a byte read, followed by a byte write::
50 S Addr Rd [A] [Data] NA S Addr Wr [A] Data [A] P
56 The following modifications to the I2C protocol can also be generated by
57 setting these flags for I2C messages. With the exception of I2C_M_NOSTART, they
58 are usually only needed to work around device issues:
61 Normally message is interrupted immediately if there is [NA] from the
62 client. Setting this flag treats any [NA] as [A], and all of
64 These messages may still fail to SCL lo->hi timeout.
67 In a read message, master A/NA bit is skipped.
70 In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some
71 point. For example, setting I2C_M_NOSTART on the second partial message
72 generates something like::
74 S Addr Rd [A] [Data] NA Data [A] P
76 If you set the I2C_M_NOSTART variable for the first partial message,
77 we do not generate Addr, but we do generate the start condition S.
78 This will probably confuse all other clients on your bus, so don't
81 This is often used to gather transmits from multiple data buffers in
82 system memory into something that appears as a single transfer to the
83 I2C device but may also be used between direction changes by some
87 This toggles the Rd/Wr flag. That is, if you want to do a write, but
88 need to emit an Rd instead of a Wr, or vice versa, you set this
91 S Addr Rd [A] Data [A] Data [A] ... [A] Data [A] P
94 Force a stop condition (P) after the message. Some I2C related protocols
95 like SCCB require that. Normally, you really don't want to get interrupted
96 between the messages of one transfer.