1 * Renesas R-Car Compare Match Timer (CMT)
3 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
4 inputs and programmable compare match.
6 Channels share hardware resources but their counter and compare match value
7 are independent. A particular CMT instance can implement only a subset of the
8 channels supported by the CMT model. Channel indices represent the hardware
9 position of the channel in the CMT and don't match the channel numbers in the
14 - compatible: must contain one of the following.
15 - "renesas,cmt-32" for the 32-bit CMT
16 (CMT0 on sh7372, sh73a0 and r8a7740)
17 - "renesas,cmt-32-fast" for the 32-bit CMT with fast clock support
18 (CMT[234] on sh7372, sh73a0 and r8a7740)
19 - "renesas,cmt-48" for the 48-bit CMT
20 (CMT1 on sh7372, sh73a0 and r8a7740)
21 - "renesas,cmt-48-gen2" for the second generation 48-bit CMT
22 (CMT[01] on r8a73a4, r8a7790 and r8a7791)
24 - reg: base address and length of the registers block for the timer module.
25 - interrupts: interrupt-specifier for the timer, one per channel.
26 - clocks: a list of phandle + clock-specifier pairs, one for each entry
28 - clock-names: must contain "fck" for the functional clock.
30 - renesas,channels-mask: bitmask of the available channels.
33 Example: R8A7790 (R-Car H2) CMT0 node
35 CMT0 on R8A7790 implements hardware channels 5 and 6 only and names
36 them channels 0 and 1 in the documentation.
38 cmt0: timer@ffca0000 {
39 compatible = "renesas,cmt-48-gen2";
40 reg = <0 0xffca0000 0 0x1004>;
41 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
42 <0 142 IRQ_TYPE_LEVEL_HIGH>;
43 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
46 renesas,channels-mask = <0x60>;