1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 # Copyright 2019 Linaro Ltd.
5 $id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: QCOM SoC Temperature Sensor (TSENS)
11 - Amit Kucheria <amitk@kernel.org>
14 QCOM SoCs have TSENS IP to allow temperature measurement. There are currently
15 three distinct major versions of the IP that is supported by a single driver.
16 The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures
17 everything before v1 when there was no versioning information.
22 - description: msm8960 TSENS based
28 - description: v0.1 of TSENS
35 - const: qcom,tsens-v0_1
37 - description: v1 of TSENS
42 - const: qcom,tsens-v1
44 - description: v2 of TSENS
63 - const: qcom,tsens-v2
65 - description: v2 of TSENS with combined interrupt
71 - description: TM registers
72 - description: SROT registers
86 Reference to an nvmem node for the calibration data
98 Number of sensors enabled on this platform
99 $ref: /schemas/types.yaml#/definitions/uint32
103 "#thermal-sensor-cells":
106 Number of cells required to uniquely identify the thermal sensors. Since
107 we have multiple sensors this is set to 1
113 - "#thermal-sensor-cells"
135 - description: Combined interrupt if upper or lower threshold crossed
151 - qcom,sc8280xp-tsens
164 - description: Combined interrupt if upper or lower threshold crossed
165 - description: Interrupt if critical threshold crossed
181 - description: Combined interrupt if upper, lower or critical thresholds crossed
200 additionalProperties: false
204 #include <dt-bindings/interrupt-controller/arm-gic.h>
205 // Example msm9860 based SoC (ipq8064):
206 gcc: clock-controller {
210 tsens: thermal-sensor {
211 compatible = "qcom,ipq8064-tsens";
213 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
214 nvmem-cell-names = "calib", "calib_backup";
215 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
216 interrupt-names = "uplow";
218 #qcom,sensors = <11>;
219 #thermal-sensor-cells = <1>;
224 #include <dt-bindings/interrupt-controller/arm-gic.h>
225 // Example 1 (legacy: for pre v1 IP):
226 tsens1: thermal-sensor@900000 {
227 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
228 reg = <0x4a9000 0x1000>, /* TM */
229 <0x4a8000 0x1000>; /* SROT */
231 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
232 nvmem-cell-names = "calib", "calib_sel";
234 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
235 interrupt-names = "uplow";
238 #thermal-sensor-cells = <1>;
242 #include <dt-bindings/interrupt-controller/arm-gic.h>
243 // Example 2 (for any platform containing v1 of the TSENS IP):
244 tsens2: thermal-sensor@4a9000 {
245 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
246 reg = <0x004a9000 0x1000>, /* TM */
247 <0x004a8000 0x1000>; /* SROT */
249 nvmem-cells = <&tsens_caldata>;
250 nvmem-cell-names = "calib";
252 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
253 interrupt-names = "uplow";
255 #qcom,sensors = <10>;
256 #thermal-sensor-cells = <1>;
260 #include <dt-bindings/interrupt-controller/arm-gic.h>
261 // Example 3 (for any platform containing v2 of the TSENS IP):
262 tsens3: thermal-sensor@c263000 {
263 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
264 reg = <0xc263000 0x1ff>,
267 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
269 interrupt-names = "uplow", "critical";
271 #qcom,sensors = <13>;
272 #thermal-sensor-cells = <1>;
276 #include <dt-bindings/interrupt-controller/arm-gic.h>
277 // Example 4 (for any IPQ8074 based SoC-s):
278 tsens4: thermal-sensor@4a9000 {
279 compatible = "qcom,ipq8074-tsens";
280 reg = <0x4a9000 0x1000>,
283 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "combined";
286 #qcom,sensors = <16>;
287 #thermal-sensor-cells = <1>;