1 Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
4 - compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
5 "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" or
7 - reg : The register base for the controller. For "mscc,<soc>-spi", a second
8 register set is required (named ICPU_CFG:SPI_MST)
9 - interrupts : One interrupt, used by the controller.
10 - #address-cells : <1>, as required by generic SPI binding.
11 - #size-cells : <0>, also as required by generic SPI binding.
12 - clocks : phandles for the clocks, see the description of clock-names below.
13 The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
14 is optional. If a single clock is specified but no clock-name, it is the
15 "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
18 - clock-names : Contains the names of the clocks:
19 "ssi_clk", for the core clock used to generate the external SPI clock.
20 "pclk", the interface clock, required for register access. If a clock domain
21 used to enable this clock then it should be named "pclk_clkdomain".
22 - cs-gpios : Specifies the gpio pins to be used for chipselects.
23 - num-cs : The number of chipselects. If omitted, this will default to 4.
24 - reg-io-width : The I/O register width (in bytes) implemented by this
25 device. Supported values are 2 or 4 (the default).
26 - dmas : Phandle + identifiers of Tx and Rx DMA channels.
27 - dma-names : Contains the names of the DMA channels. Must be "tx" and "rx".
28 - resets : contains an entry for each entry in reset-names.
29 See ../reset/reset.txt for details.
30 - reset-names : must contain "spi"
32 Child nodes as per the generic SPI binding.
37 compatible = "snps,dw-apb-ssi";
38 reg = <0xfff00000 0x1000>;
39 interrupts = <0 154 4>;
42 clocks = <&spi_m_clk>;
44 cs-gpios = <&gpio0 13 0>,
46 resets = <&rst SPIM0_RST>;