1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Quad SPI controller
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
18 const: xlnx,versal-ospi-1.0
31 - xlnx,versal-ospi-1.0
33 - const: cdns,qspi-nor
34 - const: cdns,qspi-nor
38 - description: the controller register set
39 - description: the controller data area
49 Size of the data FIFO in words.
50 $ref: "/schemas/types.yaml#/definitions/uint32"
55 $ref: /schemas/types.yaml#/definitions/uint32
57 Bus width of the data FIFO in bytes.
61 $ref: /schemas/types.yaml#/definitions/uint32
63 32-bit indirect AHB trigger address.
68 Flag to indicate whether decoder is used to select different chip select
69 for different memory regions.
74 Flag to indicate that QSPI return clock is used to latch the read
75 data rather than the QSPI clock. Make sure that QSPI return clock
76 is populated on the board before using this property.
88 enum: [ qspi, qspi-ocp ]
97 - cdns,trigger-address
101 unevaluatedProperties: false
106 compatible = "cdns,qspi-nor";
107 #address-cells = <1>;
109 reg = <0xff705000 0x1000>,
111 interrupts = <0 151 4>;
112 clocks = <&qspi_clk>;
113 cdns,fifo-depth = <128>;
114 cdns,fifo-width = <4>;
115 cdns,trigger-address = <0x00000000>;
116 resets = <&rst 0x1>, <&rst 0x2>;
117 reset-names = "qspi", "qspi-ocp";
120 compatible = "jedec,spi-nor";