1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/serial/renesas,scif.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Renesas Serial Communication Interface with FIFO (SCIF)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
20 - renesas,scif-r7s72100 # RZ/A1H
21 - const: renesas,scif # generic SCIF compatible UART
25 - renesas,scif-r7s9210 # RZ/A2
29 - renesas,scif-r8a7778 # R-Car M1
30 - renesas,scif-r8a7779 # R-Car H1
31 - const: renesas,rcar-gen1-scif # R-Car Gen1
32 - const: renesas,scif # generic SCIF compatible UART
36 - renesas,scif-r8a7742 # RZ/G1H
37 - renesas,scif-r8a7743 # RZ/G1M
38 - renesas,scif-r8a7744 # RZ/G1N
39 - renesas,scif-r8a7745 # RZ/G1E
40 - renesas,scif-r8a77470 # RZ/G1C
41 - renesas,scif-r8a7790 # R-Car H2
42 - renesas,scif-r8a7791 # R-Car M2-W
43 - renesas,scif-r8a7792 # R-Car V2H
44 - renesas,scif-r8a7793 # R-Car M2-N
45 - renesas,scif-r8a7794 # R-Car E2
46 - const: renesas,rcar-gen2-scif # R-Car Gen2 and RZ/G1
47 - const: renesas,scif # generic SCIF compatible UART
51 - renesas,scif-r8a774a1 # RZ/G2M
52 - renesas,scif-r8a774b1 # RZ/G2N
53 - renesas,scif-r8a774c0 # RZ/G2E
54 - renesas,scif-r8a774e1 # RZ/G2H
55 - renesas,scif-r8a7795 # R-Car H3
56 - renesas,scif-r8a7796 # R-Car M3-W
57 - renesas,scif-r8a77961 # R-Car M3-W+
58 - renesas,scif-r8a77965 # R-Car M3-N
59 - renesas,scif-r8a77970 # R-Car V3M
60 - renesas,scif-r8a77980 # R-Car V3H
61 - renesas,scif-r8a77990 # R-Car E3
62 - renesas,scif-r8a77995 # R-Car D3
63 - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2
64 - const: renesas,scif # generic SCIF compatible UART
68 - renesas,scif-r8a779a0 # R-Car V3U
69 - renesas,scif-r8a779f0 # R-Car S4-8
70 - const: renesas,rcar-gen4-scif # R-Car Gen4
71 - const: renesas,scif # generic SCIF compatible UART
75 - renesas,scif-r9a07g044 # RZ/G2{L,LC}
79 - renesas,scif-r9a07g043 # RZ/G2UL and RZ/Five
80 - renesas,scif-r9a07g054 # RZ/V2L
81 - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback
89 - description: A combined interrupt
91 - description: Error interrupt
92 - description: Receive buffer full interrupt
93 - description: Transmit buffer empty interrupt
94 - description: Break interrupt
96 - description: Error interrupt
97 - description: Receive buffer full interrupt
98 - description: Transmit buffer empty interrupt
99 - description: Break interrupt
100 - description: Data Ready interrupt
101 - description: Transmit End interrupt
127 - fck # UART functional clock
128 - sck # optional external clock input
129 - brg_int # optional internal clock source for BRG frequency divider
130 - scif_clk # optional external clock source for BRG frequency divider
142 Must contain a list of pairs of references to DMA specifiers, one for
143 transmission, and one for reception.
166 - renesas,rcar-gen2-scif
167 - renesas,rcar-gen3-scif
168 - renesas,rcar-gen4-scif
169 - renesas,scif-r9a07g044
174 unevaluatedProperties: false
178 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
179 #include <dt-bindings/interrupt-controller/arm-gic.h>
180 #include <dt-bindings/power/r8a7791-sysc.h>
185 scif0: serial@e6e60000 {
186 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
188 reg = <0xe6e60000 64>;
189 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
192 clock-names = "fck", "brg_int", "scif_clk";
193 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>;
194 dma-names = "tx", "rx", "tx", "rx";
195 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;