Documentation/devicetree/bindings/riscv/cpus.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: RISC-V CPUs
   8
   9 maintainers:
  10   - Paul Walmsley <paul.walmsley@sifive.com>
  11   - Palmer Dabbelt <palmer@sifive.com>
  12   - Conor Dooley <conor@kernel.org>
  13
  14 description: |
  15   This document uses some terminology common to the RISC-V community
  16   that is not widely used, the definitions of which are listed here:
  17
  18   hart: A hardware execution context, which contains all the state
  19   mandated by the RISC-V ISA: a PC and some registers.  This
  20   terminology is designed to disambiguate software's view of execution
  21   contexts from any particular microarchitectural implementation
  22   strategy.  For example, an Intel laptop containing one socket with
  23   two cores, each of which has two hyperthreads, could be described as
  24   having four harts.
  25
  26 allOf:
  27   - $ref: /schemas/cpu.yaml#
  28   - $ref: extensions.yaml
  29
  30 properties:
  31   compatible:
  32     oneOf:
  33       - items:
  34           - enum:
  35               - andestech,ax45mp
  36               - canaan,k210
  37               - sifive,bullet0
  38               - sifive,e5
  39               - sifive,e7
  40               - sifive,e71
  41               - sifive,rocket0
  42               - sifive,s7
  43               - sifive,u5
  44               - sifive,u54
  45               - sifive,u7
  46               - sifive,u74
  47               - sifive,u74-mc
  48               - thead,c906
  49               - thead,c910
  50           - const: riscv
  51       - items:
  52           - enum:
  53               - sifive,e51
  54               - sifive,u54-mc
  55           - const: sifive,rocket0
  56           - const: riscv
  57       - const: riscv    # Simulator only
  58     description:
  59       Identifies that the hart uses the RISC-V instruction set
  60       and identifies the type of the hart.
  61
  62   mmu-type:
  63     description:
  64       Identifies the MMU address translation mode used on this
  65       hart.  These values originate from the RISC-V Privileged
  66       Specification document, available from
  67       https://riscv.org/specifications/
  68     $ref: /schemas/types.yaml#/definitions/string
  69     enum:
  70       - riscv,sv32
  71       - riscv,sv39
  72       - riscv,sv48
  73       - riscv,sv57
  74       - riscv,none
  75
  76   riscv,cbom-block-size:
  77     $ref: /schemas/types.yaml#/definitions/uint32
  78     description:
  79       The blocksize in bytes for the Zicbom cache operations.
  80
  81   riscv,cboz-block-size:
  82     $ref: /schemas/types.yaml#/definitions/uint32
  83     description:
  84       The blocksize in bytes for the Zicboz cache operations.
  85
  86   # RISC-V has multiple properties for cache op block sizes as the sizes
  87   # differ between individual CBO extensions
  88   cache-op-block-size: false
  89   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
  90   timebase-frequency: false
  91
  92   interrupt-controller:
  93     type: object
  94     additionalProperties: false
  95     description: Describes the CPU's local interrupt controller
  96
  97     properties:
  98       '#interrupt-cells':
  99         const: 1
 100
 101       compatible:
 102         const: riscv,cpu-intc
 103
 104       interrupt-controller: true
 105
 106     required:
 107       - '#interrupt-cells'
 108       - compatible
 109       - interrupt-controller
 110
 111   cpu-idle-states:
 112     $ref: /schemas/types.yaml#/definitions/phandle-array
 113     items:
 114       maxItems: 1
 115     description: |
 116       List of phandles to idle state nodes supported
 117       by this hart (see ./idle-states.yaml).
 118
 119   capacity-dmips-mhz:
 120     description:
 121       u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
 122       DMIPS/MHz, relative to highest capacity-dmips-mhz
 123       in the system.
 124
 125 anyOf:
 126   - required:
 127       - riscv,isa
 128   - required:
 129       - riscv,isa-base
 130
 131 dependencies:
 132   riscv,isa-base: [ "riscv,isa-extensions" ]
 133   riscv,isa-extensions: [ "riscv,isa-base" ]
 134
 135 required:
 136   - interrupt-controller
 137
 138 unevaluatedProperties: false
 139
 140 examples:
 141   - |
 142     // Example 1: SiFive Freedom U540G Development Kit
 143     cpus {
 144         #address-cells = <1>;
 145         #size-cells = <0>;
 146         timebase-frequency = <1000000>;
 147         cpu@0 {
 148                 clock-frequency = <0>;
 149                 compatible = "sifive,rocket0", "riscv";
 150                 device_type = "cpu";
 151                 i-cache-block-size = <64>;
 152                 i-cache-sets = <128>;
 153                 i-cache-size = <16384>;
 154                 reg = <0>;
 155                 riscv,isa-base = "rv64i";
 156                 riscv,isa-extensions = "i", "m", "a", "c";
 157
 158                 cpu_intc0: interrupt-controller {
 159                         #interrupt-cells = <1>;
 160                         compatible = "riscv,cpu-intc";
 161                         interrupt-controller;
 162                 };
 163         };
 164         cpu@1 {
 165                 clock-frequency = <0>;
 166                 compatible = "sifive,rocket0", "riscv";
 167                 d-cache-block-size = <64>;
 168                 d-cache-sets = <64>;
 169                 d-cache-size = <32768>;
 170                 d-tlb-sets = <1>;
 171                 d-tlb-size = <32>;
 172                 device_type = "cpu";
 173                 i-cache-block-size = <64>;
 174                 i-cache-sets = <64>;
 175                 i-cache-size = <32768>;
 176                 i-tlb-sets = <1>;
 177                 i-tlb-size = <32>;
 178                 mmu-type = "riscv,sv39";
 179                 reg = <1>;
 180                 tlb-split;
 181                 riscv,isa-base = "rv64i";
 182                 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
 183
 184                 cpu_intc1: interrupt-controller {
 185                         #interrupt-cells = <1>;
 186                         compatible = "riscv,cpu-intc";
 187                         interrupt-controller;
 188                 };
 189         };
 190     };
 191
 192   - |
 193     // Example 2: Spike ISA Simulator with 1 Hart
 194     cpus {
 195         #address-cells = <1>;
 196         #size-cells = <0>;
 197         cpu@0 {
 198                 device_type = "cpu";
 199                 reg = <0>;
 200                 compatible = "riscv";
 201                 mmu-type = "riscv,sv48";
 202                 riscv,isa-base = "rv64i";
 203                 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
 204
 205                 interrupt-controller {
 206                         #interrupt-cells = <1>;
 207                         interrupt-controller;
 208                         compatible = "riscv,cpu-intc";
 209                 };
 210         };
 211     };
 212 ...