Documentation/devicetree/bindings/riscv/cpus.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: RISC-V CPUs
   8
   9 maintainers:
  10   - Paul Walmsley <paul.walmsley@sifive.com>
  11   - Palmer Dabbelt <palmer@sifive.com>
  12   - Conor Dooley <conor@kernel.org>
  13
  14 description: |
  15   This document uses some terminology common to the RISC-V community
  16   that is not widely used, the definitions of which are listed here:
  17
  18   hart: A hardware execution context, which contains all the state
  19   mandated by the RISC-V ISA: a PC and some registers.  This
  20   terminology is designed to disambiguate software's view of execution
  21   contexts from any particular microarchitectural implementation
  22   strategy.  For example, an Intel laptop containing one socket with
  23   two cores, each of which has two hyperthreads, could be described as
  24   having four harts.
  25
  26 allOf:
  27   - $ref: /schemas/cpu.yaml#
  28   - $ref: extensions.yaml
  29
  30 properties:
  31   compatible:
  32     oneOf:
  33       - items:
  34           - enum:
  35               - andestech,ax45mp
  36               - canaan,k210
  37               - sifive,bullet0
  38               - sifive,e5
  39               - sifive,e7
  40               - sifive,e71
  41               - sifive,rocket0
  42               - sifive,s7
  43               - sifive,u5
  44               - sifive,u54
  45               - sifive,u7
  46               - sifive,u74
  47               - sifive,u74-mc
  48               - thead,c906
  49               - thead,c910
  50           - const: riscv
  51       - items:
  52           - enum:
  53               - sifive,e51
  54               - sifive,u54-mc
  55           - const: sifive,rocket0
  56           - const: riscv
  57       - const: riscv    # Simulator only
  58     description:
  59       Identifies that the hart uses the RISC-V instruction set
  60       and identifies the type of the hart.
  61
  62   mmu-type:
  63     description:
  64       Identifies the MMU address translation mode used on this
  65       hart.  These values originate from the RISC-V Privileged
  66       Specification document, available from
  67       https://riscv.org/specifications/
  68     $ref: /schemas/types.yaml#/definitions/string
  69     enum:
  70       - riscv,sv32
  71       - riscv,sv39
  72       - riscv,sv48
  73       - riscv,sv57
  74       - riscv,none
  75
  76   riscv,cbom-block-size:
  77     $ref: /schemas/types.yaml#/definitions/uint32
  78     description:
  79       The blocksize in bytes for the Zicbom cache operations.
  80
  81   riscv,cboz-block-size:
  82     $ref: /schemas/types.yaml#/definitions/uint32
  83     description:
  84       The blocksize in bytes for the Zicboz cache operations.
  85
  86   # RISC-V has multiple properties for cache op block sizes as the sizes
  87   # differ between individual CBO extensions
  88   cache-op-block-size: false
  89   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
  90   timebase-frequency: false
  91
  92   interrupt-controller:
  93     type: object
  94     description: Describes the CPU's local interrupt controller
  95
  96     properties:
  97       '#interrupt-cells':
  98         const: 1
  99
 100       compatible:
 101         const: riscv,cpu-intc
 102
 103       interrupt-controller: true
 104
 105     required:
 106       - '#interrupt-cells'
 107       - compatible
 108       - interrupt-controller
 109
 110   cpu-idle-states:
 111     $ref: /schemas/types.yaml#/definitions/phandle-array
 112     items:
 113       maxItems: 1
 114     description: |
 115       List of phandles to idle state nodes supported
 116       by this hart (see ./idle-states.yaml).
 117
 118   capacity-dmips-mhz:
 119     description:
 120       u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
 121       DMIPS/MHz, relative to highest capacity-dmips-mhz
 122       in the system.
 123
 124 anyOf:
 125   - required:
 126       - riscv,isa
 127   - required:
 128       - riscv,isa-base
 129
 130 dependencies:
 131   riscv,isa-base: [ "riscv,isa-extensions" ]
 132   riscv,isa-extensions: [ "riscv,isa-base" ]
 133
 134 required:
 135   - interrupt-controller
 136
 137 unevaluatedProperties: false
 138
 139 examples:
 140   - |
 141     // Example 1: SiFive Freedom U540G Development Kit
 142     cpus {
 143         #address-cells = <1>;
 144         #size-cells = <0>;
 145         timebase-frequency = <1000000>;
 146         cpu@0 {
 147                 clock-frequency = <0>;
 148                 compatible = "sifive,rocket0", "riscv";
 149                 device_type = "cpu";
 150                 i-cache-block-size = <64>;
 151                 i-cache-sets = <128>;
 152                 i-cache-size = <16384>;
 153                 reg = <0>;
 154                 riscv,isa-base = "rv64i";
 155                 riscv,isa-extensions = "i", "m", "a", "c";
 156
 157                 cpu_intc0: interrupt-controller {
 158                         #interrupt-cells = <1>;
 159                         compatible = "riscv,cpu-intc";
 160                         interrupt-controller;
 161                 };
 162         };
 163         cpu@1 {
 164                 clock-frequency = <0>;
 165                 compatible = "sifive,rocket0", "riscv";
 166                 d-cache-block-size = <64>;
 167                 d-cache-sets = <64>;
 168                 d-cache-size = <32768>;
 169                 d-tlb-sets = <1>;
 170                 d-tlb-size = <32>;
 171                 device_type = "cpu";
 172                 i-cache-block-size = <64>;
 173                 i-cache-sets = <64>;
 174                 i-cache-size = <32768>;
 175                 i-tlb-sets = <1>;
 176                 i-tlb-size = <32>;
 177                 mmu-type = "riscv,sv39";
 178                 reg = <1>;
 179                 tlb-split;
 180                 riscv,isa-base = "rv64i";
 181                 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
 182
 183                 cpu_intc1: interrupt-controller {
 184                         #interrupt-cells = <1>;
 185                         compatible = "riscv,cpu-intc";
 186                         interrupt-controller;
 187                 };
 188         };
 189     };
 190
 191   - |
 192     // Example 2: Spike ISA Simulator with 1 Hart
 193     cpus {
 194         #address-cells = <1>;
 195         #size-cells = <0>;
 196         cpu@0 {
 197                 device_type = "cpu";
 198                 reg = <0>;
 199                 compatible = "riscv";
 200                 mmu-type = "riscv,sv48";
 201                 riscv,isa-base = "rv64i";
 202                 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
 203
 204                 interrupt-controller {
 205                         #interrupt-cells = <1>;
 206                         interrupt-controller;
 207                         compatible = "riscv,cpu-intc";
 208                 };
 209         };
 210     };
 211 ...