Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: StarFive JH7100 Pin Controller
   8
   9 description: |
  10   Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
  11
  12   Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63]
  13   and PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141] can be multiplexed and have
  14   configurable bias, drive strength, schmitt trigger etc. The SoC has an
  15   interesting 2-layered approach to pin muxing best illustrated by the diagram
  16   below.
  17
  18                           Signal group 0, 1, ... or 6
  19                                  ___|___
  20                                 |       |
  21     LCD output -----------------|       |
  22     CMOS Camera interface ------|       |--- PAD_GPIO[0]
  23     Ethernet PHY interface -----|  MUX  |--- PAD_GPIO[1]
  24       ...                       |       |      ...
  25                                 |       |--- PAD_GPIO[63]
  26      -------- GPIO0 ------------|       |
  27     |  -------|-- GPIO1 --------|       |--- PAD_FUNC_SHARE[0]
  28     | |       |   |             |       |--- PAD_FUNC_SHARE[1]
  29     | |       |   |  ...        |       |       ...
  30     | |       |   |             |       |--- PAD_FUNC_SHARE[141]
  31     | |  -----|---|-- GPIO63 ---|       |
  32     | | |     |   |   |          -------
  33     UART0     UART1 --
  34
  35
  36   The big MUX in the diagram only has 7 different ways of mapping peripherals
  37   on the left to pins on the right. StarFive calls the 7 configurations "signal
  38   groups".
  39   However some peripherals have their I/O go through the 64 "GPIOs". The
  40   diagram only shows UART0 and UART1, but this also includes a number of other
  41   UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64
  42   GPIOs such that any GPIO can be set up to be controlled by any of the
  43   peripherals.
  44   Note that signal group 0 doesn't map any of the GPIOs to pins, and only
  45   signal group 1 maps the GPIOs to the pins named PAD_GPIO[0] to PAD_GPIO[63].
  46
  47 maintainers:
  48   - Emil Renner Berthing <kernel@esmil.dk>
  49   - Drew Fustini <drew@beagleboard.org>
  50
  51 properties:
  52   compatible:
  53     const: starfive,jh7100-pinctrl
  54
  55   reg:
  56     minItems: 2
  57     maxItems: 2
  58
  59   reg-names:
  60     items:
  61       - const: gpio
  62       - const: padctl
  63
  64   clocks:
  65     maxItems: 1
  66
  67   resets:
  68     maxItems: 1
  69
  70   gpio-controller: true
  71
  72   "#gpio-cells":
  73     const: 2
  74
  75   interrupts:
  76     maxItems: 1
  77     description: The GPIO parent interrupt.
  78
  79   interrupt-controller: true
  80
  81   "#interrupt-cells":
  82     const: 2
  83
  84   starfive,signal-group:
  85     description: |
  86       Select one of the 7 signal groups. If this property is not set it
  87       defaults to the configuration already chosen by the earlier boot stages.
  88     $ref: /schemas/types.yaml#/definitions/uint32
  89     enum: [0, 1, 2, 3, 4, 5, 6]
  90
  91   starfive,keep-gpiomux:
  92     description: Keep pinmux for these GPIOs from being reset at boot.
  93     $ref: /schemas/types.yaml#/definitions/uint32-array
  94
  95 required:
  96   - compatible
  97   - reg
  98   - reg-names
  99   - clocks
 100   - gpio-controller
 101   - "#gpio-cells"
 102   - interrupts
 103   - interrupt-controller
 104   - "#interrupt-cells"
 105
 106 patternProperties:
 107   '-[0-9]+$':
 108     type: object
 109     patternProperties:
 110       '-pins$':
 111         type: object
 112         description: |
 113           A pinctrl node should contain at least one subnode representing the
 114           pinctrl groups available on the machine. Each subnode will list the
 115           pins it needs, and how they should be configured, with regard to
 116           muxer configuration, bias, input enable/disable, input schmitt
 117           trigger enable/disable, slew-rate and drive strength.
 118         $ref: "/schemas/pinctrl/pincfg-node.yaml"
 119
 120         properties:
 121           pins:
 122             description: |
 123               The list of pin identifiers that properties in the node apply to.
 124               This should be set using either the PAD_GPIO or PAD_FUNC_SHARE
 125               macros.
 126               Either this or "pinmux" has to be specified, but not both.
 127             $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pins"
 128
 129           pinmux:
 130             description: |
 131               The list of GPIOs and their mux settings that properties in the
 132               node apply to. This should be set using the GPIOMUX macro.
 133               Either this or "pins" has to be specified, but not both.
 134             $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pinmux"
 135
 136           bias-disable: true
 137
 138           bias-pull-up:
 139             type: boolean
 140
 141           bias-pull-down:
 142             type: boolean
 143
 144           drive-strength:
 145             enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ]
 146
 147           input-enable: true
 148
 149           input-disable: true
 150
 151           input-schmitt-enable: true
 152
 153           input-schmitt-disable: true
 154
 155           slew-rate:
 156             maximum: 7
 157
 158           starfive,strong-pull-up:
 159             description: enable strong pull-up.
 160             type: boolean
 161
 162         additionalProperties: false
 163
 164     additionalProperties: false
 165
 166 additionalProperties: false
 167
 168 examples:
 169   - |
 170     #include <dt-bindings/clock/starfive-jh7100.h>
 171     #include <dt-bindings/reset/starfive-jh7100.h>
 172     #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
 173
 174     soc {
 175         #address-cells = <2>;
 176         #size-cells = <2>;
 177
 178         pinctrl@11910000 {
 179             compatible = "starfive,jh7100-pinctrl";
 180             reg = <0x0 0x11910000 0x0 0x10000>,
 181                   <0x0 0x11858000 0x0 0x1000>;
 182             reg-names = "gpio", "padctl";
 183             clocks = <&clkgen JH7100_CLK_GPIO_APB>;
 184             resets = <&clkgen JH7100_RSTN_GPIO_APB>;
 185             interrupts = <32>;
 186             gpio-controller;
 187             #gpio-cells = <2>;
 188             interrupt-controller;
 189             #interrupt-cells = <2>;
 190             starfive,signal-group = <6>;
 191
 192             gmac_pins_default: gmac-0 {
 193                 gtxclk-pins {
 194                     pins = <PAD_FUNC_SHARE(115)>;
 195                     bias-pull-up;
 196                     drive-strength = <35>;
 197                     input-enable;
 198                     input-schmitt-enable;
 199                     slew-rate = <0>;
 200                 };
 201                 miitxclk-pins {
 202                     pins = <PAD_FUNC_SHARE(116)>;
 203                     bias-pull-up;
 204                     drive-strength = <14>;
 205                     input-enable;
 206                     input-schmitt-disable;
 207                     slew-rate = <0>;
 208                 };
 209                 tx-pins {
 210                     pins = <PAD_FUNC_SHARE(117)>,
 211                            <PAD_FUNC_SHARE(119)>,
 212                            <PAD_FUNC_SHARE(120)>,
 213                            <PAD_FUNC_SHARE(121)>,
 214                            <PAD_FUNC_SHARE(122)>,
 215                            <PAD_FUNC_SHARE(123)>,
 216                            <PAD_FUNC_SHARE(124)>,
 217                            <PAD_FUNC_SHARE(125)>,
 218                            <PAD_FUNC_SHARE(126)>;
 219                     bias-disable;
 220                     drive-strength = <35>;
 221                     input-disable;
 222                     input-schmitt-disable;
 223                     slew-rate = <0>;
 224                 };
 225                 rxclk-pins {
 226                     pins = <PAD_FUNC_SHARE(127)>;
 227                     bias-pull-up;
 228                     drive-strength = <14>;
 229                     input-enable;
 230                     input-schmitt-disable;
 231                     slew-rate = <6>;
 232                 };
 233                 rxer-pins {
 234                     pins = <PAD_FUNC_SHARE(129)>;
 235                     bias-pull-up;
 236                     drive-strength = <14>;
 237                     input-enable;
 238                     input-schmitt-disable;
 239                     slew-rate = <0>;
 240                 };
 241                 rx-pins {
 242                     pins = <PAD_FUNC_SHARE(128)>,
 243                            <PAD_FUNC_SHARE(130)>,
 244                            <PAD_FUNC_SHARE(131)>,
 245                            <PAD_FUNC_SHARE(132)>,
 246                            <PAD_FUNC_SHARE(133)>,
 247                            <PAD_FUNC_SHARE(134)>,
 248                            <PAD_FUNC_SHARE(135)>,
 249                            <PAD_FUNC_SHARE(136)>,
 250                            <PAD_FUNC_SHARE(137)>,
 251                            <PAD_FUNC_SHARE(138)>,
 252                            <PAD_FUNC_SHARE(139)>,
 253                            <PAD_FUNC_SHARE(140)>,
 254                            <PAD_FUNC_SHARE(141)>;
 255                     bias-pull-up;
 256                     drive-strength = <14>;
 257                     input-enable;
 258                     input-schmitt-enable;
 259                     slew-rate = <0>;
 260                 };
 261             };
 262
 263             i2c0_pins_default: i2c0-0 {
 264                 i2c-pins {
 265                     pinmux = <GPIOMUX(62, GPO_LOW,
 266                               GPO_I2C0_PAD_SCK_OEN,
 267                               GPI_I2C0_PAD_SCK_IN)>,
 268                              <GPIOMUX(61, GPO_LOW,
 269                               GPO_I2C0_PAD_SDA_OEN,
 270                               GPI_I2C0_PAD_SDA_IN)>;
 271                     bias-disable; /* external pull-up */
 272                     input-enable;
 273                     input-schmitt-enable;
 274                 };
 275             };
 276
 277             uart3_pins_default: uart3-0 {
 278                 rx-pins {
 279                     pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
 280                               GPI_UART3_PAD_SIN)>;
 281                     bias-pull-up;
 282                     input-enable;
 283                     input-schmitt-enable;
 284                 };
 285                 tx-pins {
 286                     pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
 287                               GPO_ENABLE, GPI_NONE)>;
 288                     bias-disable;
 289                     input-disable;
 290                     input-schmitt-disable;
 291                 };
 292             };
 293         };
 294
 295         gmac {
 296             pinctrl-0 = <&gmac_pins_default>;
 297             pinctrl-names = "default";
 298         };
 299
 300         i2c0 {
 301             pinctrl-0 = <&i2c0_pins_default>;
 302             pinctrl-names = "default";
 303         };
 304
 305         uart3 {
 306             pinctrl-0 = <&uart3_pins_default>;
 307             pinctrl-names = "default";
 308         };
 309     };
 310
 311 ...