1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright (C) STMicroelectronics 2019.
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: STM32 GPIO and Pin Mux/Config controller
11 - Alexandre TORGUE <alexandre.torgue@st.com>
14 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
15 controller. It controls the input/output settings on the available pins and
16 also provides ability to multiplex and configure the output of various
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
26 - st,stm32h743-pinctrl
27 - st,stm32mp157-pinctrl
28 - st,stm32mp157-z-pinctrl
36 pins-are-numbered: true
43 description: Should be phandle/offset/mask
44 - Phandle to the syscon node which includes IRQ mux selection.
45 - The offset of the IRQ mux selection register.
46 - The field mask of IRQ mux, needed if different of 0xf.
47 $ref: "/schemas/types.yaml#/definitions/phandle-array"
51 Indicates the SOC package used.
52 More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
53 $ref: /schemas/types.yaml#/definitions/uint32
76 Number of available gpios in a bank.
82 Should be a name string for this bank as specified in the datasheet.
83 $ref: "/schemas/types.yaml#/definitions/string"
100 Should correspond to the EXTI IOport selection (EXTI line used
101 to select GPIOs as interrupts).
102 $ref: "/schemas/types.yaml#/definitions/uint32"
119 A pinctrl node should contain at least one subnode representing the
120 pinctrl group available on the machine. Each subnode will list the
121 pins it needs, and how they should be configured, with regard to muxer
122 configuration, pullups, drive, output high/low and output speed.
125 $ref: "/schemas/types.yaml#/definitions/uint32-array"
127 Integer array, represents gpio pin number and mux setting.
128 Supported pin number and mux varies for different SoCs, and are
129 defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
130 These defines are calculated as: ((port * 16 + line) << 8) | function
132 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
133 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
134 - function: The function number, can be:
136 * 1 : Alternate Function 0
137 * 2 : Alternate Function 1
138 * 3 : Alternate Function 2
140 * 16 : Alternate Function 15
142 To simplify the usage, macro is available to generate "pinmux" field.
143 This macro is available here:
144 - include/dt-bindings/pinctrl/stm32-pinfunc.h
145 Some examples of using macro:
146 /* GPIO A9 set as alernate function 2 */
148 pinmux = <STM32_PINMUX('A', 9, AF2)>;
150 /* GPIO A9 set as GPIO */
152 pinmux = <STM32_PINMUX('A', 9, GPIO)>;
154 /* GPIO A9 set as analog */
156 pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
179 $ref: /schemas/types.yaml#/definitions/uint32
192 additionalProperties: false
196 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
197 #include <dt-bindings/mfd/stm32f4-rcc.h>
200 #address-cells = <1>;
202 compatible = "st,stm32f429-pinctrl";
203 ranges = <0 0x40020000 0x3000>;
210 resets = <&reset_ahb1 0>;
211 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
212 st,bank-name = "GPIOA";
216 //Example 2 (using gpio-ranges)
218 #address-cells = <1>;
220 compatible = "st,stm32f429-pinctrl";
221 ranges = <0 0x50020000 0x3000>;
227 reg = <0x1000 0x400>;
228 resets = <&reset_ahb1 0>;
229 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
230 st,bank-name = "GPIOB";
231 gpio-ranges = <&pinctrl 0 0 16>;
237 reg = <0x2000 0x400>;
238 resets = <&reset_ahb1 0>;
239 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
240 st,bank-name = "GPIOC";
242 gpio-ranges = <&pinctrl 0 16 3>,
247 //Example 3 pin groups
249 usart1_pins_a: usart1-0 {
251 pinmux = <STM32_PINMUX('A', 9, AF7)>;
257 pinmux = <STM32_PINMUX('A', 10, AF7)>;
264 pinctrl-0 = <&usart1_pins_a>;
265 pinctrl-names = "default";