1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6375-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SM6375 TLMM block
10 - Konrad Dybcio <konrad.dybcio@somainline.org>
13 This binding describes the Top Level Mode Multiplexer (TLMM) block found
14 in the SM6375 platform.
17 - $ref: "pinctrl.yaml#"
18 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
22 const: qcom,sm6375-tlmm
28 interrupt-controller: true
29 '#interrupt-cells': true
31 gpio-reserved-ranges: true
40 additionalProperties: false
45 - $ref: "#/$defs/qcom-sm6375-tlmm-state"
48 $ref: "#/$defs/qcom-sm6375-tlmm-state"
49 additionalProperties: false
52 qcom-sm6375-tlmm-state:
55 Pinctrl node's client devices use subnodes for desired pin configuration.
56 Client device subnodes use below standard properties.
57 $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
62 List of gpio pins affected by the properties specified in this
66 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-6])$"
67 - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
74 Specify the alternative function to be configured for the specified
77 enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
78 atest_char2, atest_char3, atest_tsens, atest_tsens2,
79 atest_usb1, atest_usb10, atest_usb11, atest_usb12,
80 atest_usb13, atest_usb2, atest_usb20, atest_usb21,
81 atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
82 cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
83 cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist,
84 ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd,
85 gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio,
86 gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext,
87 m_voc, mclk, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
88 mdp_vsync3, mi2s_0, mi2s_1, mi2s_2, mss_lte, nav_gpio,
89 nav_pps, pa_indicator, phase_flag0, phase_flag1, phase_flag10,
90 phase_flag11, phase_flag12, phase_flag13, phase_flag14,
91 phase_flag15, phase_flag16, phase_flag17, phase_flag18,
92 phase_flag19, phase_flag2, phase_flag20, phase_flag21,
93 phase_flag22, phase_flag23, phase_flag24, phase_flag25,
94 phase_flag26, phase_flag27, phase_flag28, phase_flag29,
95 phase_flag3, phase_flag30, phase_flag31, phase_flag4,
96 phase_flag5, phase_flag6, phase_flag7, phase_flag8,
97 phase_flag9, pll_bist, pll_bypassnl, pll_clk, pll_reset,
98 prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
99 qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11,
100 qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15,
101 qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,
102 qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable,
103 qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
104 qlink1_wmss, qup00, qup01, qup02, qup10, qup11_f1, qup11_f2,
105 qup12, qup13_f1, qup13_f2, qup14, sd_write, sdc1_tb, sdc2_tb,
106 sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
107 tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset,
108 uim2_clk, uim2_data, uim2_present, uim2_reset, usb2phy_ac,
109 usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
110 wlan2_adc0, wlan2_adc1 ]
125 additionalProperties: false
129 #include <dt-bindings/interrupt-controller/arm-gic.h>
131 compatible = "qcom,sm6375-tlmm";
132 reg = <0x00500000 0x800000>;
133 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
136 interrupt-controller;
137 #interrupt-cells = <2>;
138 gpio-ranges = <&tlmm 0 0 157>;
140 gpio-wo-subnode-state {
145 uart-w-subnodes-state {
148 function = "qup13_f2";
154 function = "qup13_f2";