1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SC7280 TLMM block
10 - Rajendra Nayak <rnayak@codeaurora.org>
13 This binding describes the Top Level Mode Multiplexer block found in the
18 const: qcom,sc7280-pinctrl
24 description: Specifies the TLMM summary IRQ
27 interrupt-controller: true
31 Specifies the PIN numbers and Flags, as defined in defined in
32 include/dt-bindings/interrupt-controller/irq.h
38 description: Specifying the pin number and flags, as defined in
39 include/dt-bindings/gpio/gpio.h
47 #PIN CONFIGURATION NODES
52 Pinctrl node's client devices use subnodes for desired pin configuration.
53 Client device subnodes use below standard properties.
58 List of gpio pins affected by the properties specified in this
62 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$"
63 - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
64 sdc2_cmd, sdc2_data, ufs_reset ]
70 Specify the alternative function to be configured for the specified
73 enum: [ atest_char, atest_char0, atest_char1, atest_char2,
74 atest_char3, atest_usb0, atest_usb00, atest_usb01,
75 atest_usb02, atest_usb03, atest_usb1, atest_usb10,
76 atest_usb11, atest_usb12, atest_usb13, audio_ref,
77 cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
78 cci_timer2, cci_timer3, cci_timer4, cmu_rng0, cmu_rng1,
79 cmu_rng2, cmu_rng3, coex_uart1, cri_trng, cri_trng0,
80 cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, dp_hot,
81 dp_lcd, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
82 gpio, host2wlan_sol, ibi_i3c, jitter_bist, lpass_slimbus,
83 mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
84 mdp_vsync4, mdp_vsync5, mi2s0_data0, mi2s0_data1, mi2s0_sck,
85 mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
86 mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0,
87 mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2,
88 mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7,
89 mss_grfc8, mss_grfc9, nav_gpio0, nav_gpio1, nav_gpio2,
90 pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag,
91 pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc,
92 qdss, qdss_cti, qlink0_enable, qlink0_request, qlink0_wmss,
93 qlink1_enable, qlink1_request, qlink1_wmss, qspi_clk, qspi_cs,
94 qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, qup06, qup07,
95 qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
96 sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sd_write,
97 sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tsense_pwm1,
98 tsense_pwm2, uim0_clk, uim0_data, uim0_present, uim0_reset,
99 uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac,
100 usb_phy, vfr_0, vfr_1, vsense_trigger ]
103 enum: [2, 4, 6, 8, 10, 12, 14, 16]
106 Selects the drive strength for the specified pins, in mA.
122 - $ref: /schemas/pinctrl/pincfg-node.yaml
126 pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$"
131 additionalProperties: false
134 - $ref: "pinctrl.yaml#"
140 - interrupt-controller
146 additionalProperties: false
150 #include <dt-bindings/interrupt-controller/arm-gic.h>
151 tlmm: pinctrl@f000000 {
152 compatible = "qcom,sc7280-pinctrl";
153 reg = <0xf000000 0x1000000>;
154 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
157 interrupt-controller;
158 #interrupt-cells = <2>;
159 gpio-ranges = <&tlmm 0 0 175>;
160 wakeup-parent = <&pdc>;
162 qup_uart5_default: qup-uart5-pins {
163 pins = "gpio46", "gpio47";
165 drive-strength = <2>;