Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt

   1 == MediaTek MT7622 pinctrl controller ==
   2
   3 Required properties for the root node:
   4  - compatible: Should be one of the following
   5                "mediatek,mt7622-pinctrl" for MT7622 SoC
   6  - reg: offset and length of the pinctrl space
   7
   8  - gpio-controller: Marks the device node as a GPIO controller.
   9  - #gpio-cells: Should be two. The first cell is the pin number and the
  10    second is the GPIO flags.
  11
  12 Please refer to pinctrl-bindings.txt in this directory for details of the
  13 common pinctrl bindings used by client devices, including the meaning of the
  14 phrase "pin configuration node".
  15
  16 MT7622 pin configuration nodes act as a container for an arbitrary number of
  17 subnodes. Each of these subnodes represents some desired configuration for a
  18 pin, a group, or a list of pins or groups. This configuration can include the
  19 mux function to select on those pin(s)/group(s), and various pin configuration
  20 parameters, such as pull-up, slew rate, etc.
  21
  22 We support 2 types of configuration nodes. Those nodes can be either pinmux
  23 nodes or pinconf nodes. Each configuration node can consist of multiple nodes
  24 describing the pinmux and pinconf options.
  25
  26 The name of each subnode doesn't matter as long as it is unique; all subnodes
  27 should be enumerated and processed purely based on their content.
  28
  29 == pinmux nodes content ==
  30
  31 The following generic properties as defined in pinctrl-bindings.txt are valid
  32 to specify in a pinmux subnode:
  33
  34 Required properties are:
  35  - groups: An array of strings. Each string contains the name of a group.
  36   Valid values for these names are listed below.
  37  - function: A string containing the name of the function to mux to the
  38   group. Valid values for function names are listed below.
  39
  40 == pinconf nodes content ==
  41
  42 The following generic properties as defined in pinctrl-bindings.txt are valid
  43 to specify in a pinconf subnode:
  44
  45 Required properties are:
  46  - pins: An array of strings. Each string contains the name of a pin.
  47   Valid values for these names are listed below.
  48  - groups: An array of strings. Each string contains the name of a group.
  49   Valid values for these names are listed below.
  50
  51 Optional properies are:
  52  bias-disable, bias-pull, bias-pull-down, input-enable,
  53  input-schmitt-enable, input-schmitt-disable, output-enable
  54  output-low, output-high, drive-strength, slew-rate
  55
  56  Valid arguments for 'slew-rate' are '0' for no slew rate controlled and '1' for
  57  slower slew rate respectively.
  58  Valid arguments for 'drive-strength', 4, 8, 12, or 16 in mA.
  59
  60 The following specific properties as defined are valid to specify in a pinconf
  61 subnode:
  62
  63 Optional properties are:
  64  - mediatek,tdsel: An integer describing the steps for output level shifter duty
  65    cycle when asserted (high pulse width adjustment). Valid arguments are from 0
  66    to 15.
  67  - mediatek,rdsel: An integer describing the steps for input level shifter duty
  68    cycle when asserted (high pulse width adjustment). Valid arguments are from 0
  69    to 63.
  70
  71 == Valid values for pins, function and groups on MT7622 ==
  72
  73 Valid values for pins are:
  74 pins can be referenced via the pin names as the below table shown and the
  75 related physical number is also put ahead of those names which helps cross
  76 references to pins between groups to know whether pins assignment conflict
  77 happens among devices try to acquire those available pins.
  78
  79         Pin #:  Valid values for pins
  80         -----------------------------
  81         PIN 0: "GPIO_A"
  82         PIN 1: "I2S1_IN"
  83         PIN 2: "I2S1_OUT"
  84         PIN 3: "I2S_BCLK"
  85         PIN 4: "I2S_WS"
  86         PIN 5: "I2S_MCLK"
  87         PIN 6: "TXD0"
  88         PIN 7: "RXD0"
  89         PIN 8: "SPI_WP"
  90         PIN 9: "SPI_HOLD"
  91         PIN 10: "SPI_CLK"
  92         PIN 11: "SPI_MOSI"
  93         PIN 12: "SPI_MISO"
  94         PIN 13: "SPI_CS"
  95         PIN 14: "I2C_SDA"
  96         PIN 15: "I2C_SCL"
  97         PIN 16: "I2S2_IN"
  98         PIN 17: "I2S3_IN"
  99         PIN 18: "I2S4_IN"
 100         PIN 19: "I2S2_OUT"
 101         PIN 20: "I2S3_OUT"
 102         PIN 21: "I2S4_OUT"
 103         PIN 22: "GPIO_B"
 104         PIN 23: "MDC"
 105         PIN 24: "MDIO"
 106         PIN 25: "G2_TXD0"
 107         PIN 26: "G2_TXD1"
 108         PIN 27: "G2_TXD2"
 109         PIN 28: "G2_TXD3"
 110         PIN 29: "G2_TXEN"
 111         PIN 30: "G2_TXC"
 112         PIN 31: "G2_RXD0"
 113         PIN 32: "G2_RXD1"
 114         PIN 33: "G2_RXD2"
 115         PIN 34: "G2_RXD3"
 116         PIN 35: "G2_RXDV"
 117         PIN 36: "G2_RXC"
 118         PIN 37: "NCEB"
 119         PIN 38: "NWEB"
 120         PIN 39: "NREB"
 121         PIN 40: "NDL4"
 122         PIN 41: "NDL5"
 123         PIN 42: "NDL6"
 124         PIN 43: "NDL7"
 125         PIN 44: "NRB"
 126         PIN 45: "NCLE"
 127         PIN 46: "NALE"
 128         PIN 47: "NDL0"
 129         PIN 48: "NDL1"
 130         PIN 49: "NDL2"
 131         PIN 50: "NDL3"
 132         PIN 51: "MDI_TP_P0"
 133         PIN 52: "MDI_TN_P0"
 134         PIN 53: "MDI_RP_P0"
 135         PIN 54: "MDI_RN_P0"
 136         PIN 55: "MDI_TP_P1"
 137         PIN 56: "MDI_TN_P1"
 138         PIN 57: "MDI_RP_P1"
 139         PIN 58: "MDI_RN_P1"
 140         PIN 59: "MDI_RP_P2"
 141         PIN 60: "MDI_RN_P2"
 142         PIN 61: "MDI_TP_P2"
 143         PIN 62: "MDI_TN_P2"
 144         PIN 63: "MDI_TP_P3"
 145         PIN 64: "MDI_TN_P3"
 146         PIN 65: "MDI_RP_P3"
 147         PIN 66: "MDI_RN_P3"
 148         PIN 67: "MDI_RP_P4"
 149         PIN 68: "MDI_RN_P4"
 150         PIN 69: "MDI_TP_P4"
 151         PIN 70: "MDI_TN_P4"
 152         PIN 71: "PMIC_SCL"
 153         PIN 72: "PMIC_SDA"
 154         PIN 73: "SPIC1_CLK"
 155         PIN 74: "SPIC1_MOSI"
 156         PIN 75: "SPIC1_MISO"
 157         PIN 76: "SPIC1_CS"
 158         PIN 77: "GPIO_D"
 159         PIN 78: "WATCHDOG"
 160         PIN 79: "RTS3_N"
 161         PIN 80: "CTS3_N"
 162         PIN 81: "TXD3"
 163         PIN 82: "RXD3"
 164         PIN 83: "PERST0_N"
 165         PIN 84: "PERST1_N"
 166         PIN 85: "WLED_N"
 167         PIN 86: "EPHY_LED0_N"
 168         PIN 87: "AUXIN0"
 169         PIN 88: "AUXIN1"
 170         PIN 89: "AUXIN2"
 171         PIN 90: "AUXIN3"
 172         PIN 91: "TXD4"
 173         PIN 92: "RXD4"
 174         PIN 93: "RTS4_N"
 175         PIN 94: "CST4_N"
 176         PIN 95: "PWM1"
 177         PIN 96: "PWM2"
 178         PIN 97: "PWM3"
 179         PIN 98: "PWM4"
 180         PIN 99: "PWM5"
 181         PIN 100: "PWM6"
 182         PIN 101: "PWM7"
 183         PIN 102: "GPIO_E"
 184
 185 Valid values for function are:
 186         "emmc", "eth", "i2c", "i2s", "ir", "led", "flash", "pcie",
 187         "pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog"
 188
 189 Valid values for groups are:
 190 additional data is put followingly with valid value allowing us to know which
 191 applicable function and which relevant pins (in pin#) are able applied for that
 192 group.
 193
 194         Valid value                     function        pins (in pin#)
 195         -------------------------------------------------------------------------
 196         "emmc"                          "emmc"          40, 41, 42, 43, 44, 45,
 197                                                         47, 48, 49, 50
 198         "emmc_rst"                      "emmc"          37
 199         "esw"                           "eth"           51, 52, 53, 54, 55, 56,
 200                                                         57, 58, 59, 60, 61, 62,
 201                                                         63, 64, 65, 66, 67, 68,
 202                                                         69, 70
 203         "esw_p0_p1"                     "eth"           51, 52, 53, 54, 55, 56,
 204                                                         57, 58
 205         "esw_p2_p3_p4"                  "eth"           59, 60, 61, 62, 63, 64,
 206                                                         65, 66, 67, 68, 69, 70
 207         "rgmii_via_esw"                 "eth"           59, 60, 61, 62, 63, 64,
 208                                                         65, 66, 67, 68, 69, 70
 209         "rgmii_via_gmac1"               "eth"           59, 60, 61, 62, 63, 64,
 210                                                         65, 66, 67, 68, 69, 70
 211         "rgmii_via_gmac2"               "eth"           25, 26, 27, 28, 29, 30,
 212                                                         31, 32, 33, 34, 35, 36
 213         "mdc_mdio"                      "eth"           23, 24
 214         "i2c0"                          "i2c"           14, 15
 215         "i2c1_0"                        "i2c"           55, 56
 216         "i2c1_1"                        "i2c"           73, 74
 217         "i2c1_2"                        "i2c"           87, 88
 218         "i2c2_0"                        "i2c"           57, 58
 219         "i2c2_1"                        "i2c"           75, 76
 220         "i2c2_2"                        "i2c"           89, 90
 221         "i2s_in_mclk_bclk_ws"           "i2s"           3, 4, 5
 222         "i2s1_in_data"                  "i2s"           1
 223         "i2s2_in_data"                  "i2s"           16
 224         "i2s3_in_data"                  "i2s"           17
 225         "i2s4_in_data"                  "i2s"           18
 226         "i2s_out_mclk_bclk_ws"          "i2s"           3, 4, 5
 227         "i2s1_out_data"                 "i2s"           2
 228         "i2s2_out_data"                 "i2s"           19
 229         "i2s3_out_data"                 "i2s"           20
 230         "i2s4_out_data"                 "i2s"           21
 231         "ir_0_tx"                       "ir"            16
 232         "ir_1_tx"                       "ir"            59
 233         "ir_2_tx"                       "ir"            99
 234         "ir_0_rx"                       "ir"            17
 235         "ir_1_rx"                       "ir"            60
 236         "ir_2_rx"                       "ir"            100
 237         "ephy_leds"                     "led"           86, 91, 92, 93, 94
 238         "ephy0_led"                     "led"           86
 239         "ephy1_led"                     "led"           91
 240         "ephy2_led"                     "led"           92
 241         "ephy3_led"                     "led"           93
 242         "ephy4_led"                     "led"           94
 243         "wled"                          "led"           85
 244         "par_nand"                      "flash"         37, 38, 39, 40, 41, 42,
 245                                                         43, 44, 45, 46, 47, 48,
 246                                                         49, 50
 247         "snfi"                          "flash"         8, 9, 10, 11, 12, 13
 248         "spi_nor"                       "flash"         8, 9, 10, 11, 12, 13
 249         "pcie0_0_waken"                 "pcie"          14
 250         "pcie0_1_waken"                 "pcie"          79
 251         "pcie1_0_waken"                 "pcie"          14
 252         "pcie0_0_clkreq"                "pcie"          15
 253         "pcie0_1_clkreq"                "pcie"          80
 254         "pcie1_0_clkreq"                "pcie"          15
 255         "pcie0_pad_perst"               "pcie"          83
 256         "pcie1_pad_perst"               "pcie"          84
 257         "pmic_bus"                      "pmic"          71, 72
 258         "pwm_ch1_0"                     "pwm"           51
 259         "pwm_ch1_1"                     "pwm"           73
 260         "pwm_ch1_2"                     "pwm"           95
 261         "pwm_ch2_0"                     "pwm"           52
 262         "pwm_ch2_1"                     "pwm"           74
 263         "pwm_ch2_2"                     "pwm"           96
 264         "pwm_ch3_0"                     "pwm"           53
 265         "pwm_ch3_1"                     "pwm"           75
 266         "pwm_ch3_2"                     "pwm"           97
 267         "pwm_ch4_0"                     "pwm"           54
 268         "pwm_ch4_1"                     "pwm"           67
 269         "pwm_ch4_2"                     "pwm"           76
 270         "pwm_ch4_3"                     "pwm"           98
 271         "pwm_ch5_0"                     "pwm"           68
 272         "pwm_ch5_1"                     "pwm"           77
 273         "pwm_ch5_2"                     "pwm"           99
 274         "pwm_ch6_0"                     "pwm"           69
 275         "pwm_ch6_1"                     "pwm"           78
 276         "pwm_ch6_2"                     "pwm"           81
 277         "pwm_ch6_3"                     "pwm"           100
 278         "pwm_ch7_0"                     "pwm"           70
 279         "pwm_ch7_1"                     "pwm"           82
 280         "pwm_ch7_2"                     "pwm"           101
 281         "sd_0"                          "sd"            16, 17, 18, 19, 20, 21
 282         "sd_1"                          "sd"            25, 26, 27, 28, 29, 30
 283         "spic0_0"                       "spi"           63, 64, 65, 66
 284         "spic0_1"                       "spi"           79, 80, 81, 82
 285         "spic1_0"                       "spi"           67, 68, 69, 70
 286         "spic1_1"                       "spi"           73, 74, 75, 76
 287         "spic2_0_wp_hold"               "spi"           8, 9
 288         "spic2_0"                       "spi"           10, 11, 12, 13
 289         "tdm_0_out_mclk_bclk_ws"        "tdm"           8, 9, 10
 290         "tdm_0_in_mclk_bclk_ws"         "tdm"           11, 12, 13
 291         "tdm_0_out_data"                "tdm"           20
 292         "tdm_0_in_data"                 "tdm"           21
 293         "tdm_1_out_mclk_bclk_ws"        "tdm"           57, 58, 59
 294         "tdm_1_in_mclk_bclk_ws"         "tdm"           60, 61, 62
 295         "tdm_1_out_data"                "tdm"           55
 296         "tdm_1_in_data"                 "tdm"           56
 297         "uart0_0_tx_rx"                 "uart"          6, 7
 298         "uart1_0_tx_rx"                 "uart"          55, 56
 299         "uart1_0_rts_cts"               "uart"          57, 58
 300         "uart1_1_tx_rx"                 "uart"          73, 74
 301         "uart1_1_rts_cts"               "uart"          75, 76
 302         "uart2_0_tx_rx"                 "uart"          3, 4
 303         "uart2_0_rts_cts"               "uart"          1, 2
 304         "uart2_1_tx_rx"                 "uart"          51, 52
 305         "uart2_1_rts_cts"               "uart"          53, 54
 306         "uart2_2_tx_rx"                 "uart"          59, 60
 307         "uart2_2_rts_cts"               "uart"          61, 62
 308         "uart2_3_tx_rx"                 "uart"          95, 96
 309         "uart3_0_tx_rx"                 "uart"          57, 58
 310         "uart3_1_tx_rx"                 "uart"          81, 82
 311         "uart3_1_rts_cts"               "uart"          79, 80
 312         "uart4_0_tx_rx"                 "uart"          61, 62
 313         "uart4_1_tx_rx"                 "uart"          91, 92
 314         "uart4_1_rts_cts"               "uart"          93, 94
 315         "uart4_2_tx_rx"                 "uart"          97, 98
 316         "uart4_2_rts_cts"               "uart"          95, 96
 317         "watchdog"                      "watchdog"      78
 318
 319 Example:
 320
 321         pio: pinctrl@10211000 {
 322                 compatible = "mediatek,mt7622-pinctrl";
 323                 reg = <0 0x10211000 0 0x1000>;
 324                 gpio-controller;
 325                 #gpio-cells = <2>;
 326
 327                 pinctrl_eth_default: eth-default {
 328                         mux-mdio {
 329                                 groups = "mdc_mdio";
 330                                 function = "eth";
 331                                 drive-strength = <12>;
 332                         };
 333
 334                         mux-gmac2 {
 335                                 groups = "gmac2";
 336                                 function = "eth";
 337                                 drive-strength = <12>;
 338                         };
 339
 340                         mux-esw {
 341                                 groups = "esw";
 342                                 function = "eth";
 343                                 drive-strength = <8>;
 344                         };
 345
 346                         conf-mdio {
 347                                 pins = "MDC";
 348                                 bias-pull-up;
 349                         };
 350                 };
 351         };