Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: Qualcomm QMP USB3 DP PHY controller
   9
  10 maintainers:
  11   - Manu Gautam <mgautam@codeaurora.org>
  12
  13 properties:
  14   compatible:
  15     enum:
  16       - qcom,sc7180-qmp-usb3-dp-phy
  17       - qcom,sc7180-qmp-usb3-phy
  18       - qcom,sdm845-qmp-usb3-dp-phy
  19       - qcom,sdm845-qmp-usb3-phy
  20   reg:
  21     items:
  22       - description: Address and length of PHY's USB serdes block.
  23       - description: Address and length of the DP_COM control block.
  24       - description: Address and length of PHY's DP serdes block.
  25
  26   reg-names:
  27     items:
  28       - const: usb
  29       - const: dp_com
  30       - const: dp
  31
  32   "#clock-cells":
  33     enum: [ 1, 2 ]
  34
  35   "#address-cells":
  36     enum: [ 1, 2 ]
  37
  38   "#size-cells":
  39     enum: [ 1, 2 ]
  40
  41   ranges: true
  42
  43   clocks:
  44     items:
  45       - description: Phy aux clock.
  46       - description: Phy config clock.
  47       - description: 19.2 MHz ref clk.
  48       - description: Phy common block aux clock.
  49
  50   clock-names:
  51     items:
  52       - const: aux
  53       - const: cfg_ahb
  54       - const: ref
  55       - const: com_aux
  56
  57   resets:
  58     items:
  59       - description: reset of phy block.
  60       - description: phy common block reset.
  61
  62   reset-names:
  63     items:
  64       - const: phy
  65       - const: common
  66
  67   vdda-phy-supply:
  68     description:
  69       Phandle to a regulator supply to PHY core block.
  70
  71   vdda-pll-supply:
  72     description:
  73       Phandle to 1.8V regulator supply to PHY refclk pll block.
  74
  75   vddp-ref-clk-supply:
  76     description:
  77       Phandle to a regulator supply to any specific refclk pll block.
  78
  79 #Required nodes:
  80 patternProperties:
  81   "^usb3-phy@[0-9a-f]+$":
  82     type: object
  83     description:
  84       The USB3 PHY.
  85
  86     properties:
  87       reg:
  88         items:
  89           - description: Address and length of TX.
  90           - description: Address and length of RX.
  91           - description: Address and length of PCS.
  92           - description: Address and length of TX2.
  93           - description: Address and length of RX2.
  94           - description: Address and length of pcs_misc.
  95
  96       clocks:
  97         items:
  98           - description: pipe clock
  99
 100       clock-names:
 101         items:
 102           - const: pipe0
 103
 104       clock-output-names:
 105         items:
 106           - const: usb3_phy_pipe_clk_src
 107
 108       '#clock-cells':
 109         const: 0
 110
 111       '#phy-cells':
 112         const: 0
 113
 114     required:
 115       - reg
 116       - clocks
 117       - clock-names
 118       - '#clock-cells'
 119       - '#phy-cells'
 120
 121   "^dp-phy@[0-9a-f]+$":
 122     type: object
 123     description:
 124       The DP PHY.
 125
 126     properties:
 127       reg:
 128         items:
 129           - description: Address and length of TX.
 130           - description: Address and length of RX.
 131           - description: Address and length of PCS.
 132           - description: Address and length of TX2.
 133           - description: Address and length of RX2.
 134
 135       '#clock-cells':
 136         const: 1
 137
 138       '#phy-cells':
 139         const: 0
 140
 141     required:
 142       - reg
 143       - '#clock-cells'
 144       - '#phy-cells'
 145
 146 required:
 147   - compatible
 148   - reg
 149   - "#clock-cells"
 150   - "#address-cells"
 151   - "#size-cells"
 152   - ranges
 153   - clocks
 154   - clock-names
 155   - resets
 156   - reset-names
 157   - vdda-phy-supply
 158   - vdda-pll-supply
 159
 160 additionalProperties: false
 161
 162 examples:
 163   - |
 164     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 165     usb_1_qmpphy: phy-wrapper@88e9000 {
 166         compatible = "qcom,sdm845-qmp-usb3-dp-phy";
 167         reg = <0x088e9000 0x18c>,
 168               <0x088e8000 0x10>,
 169               <0x088ea000 0x40>;
 170         reg-names = "usb", "dp_com", "dp";
 171         #clock-cells = <1>;
 172         #address-cells = <1>;
 173         #size-cells = <1>;
 174         ranges = <0x0 0x088e9000 0x2000>;
 175
 176         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
 177                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 178                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
 179                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
 180         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
 181
 182         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
 183                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
 184         reset-names = "phy", "common";
 185
 186         vdda-phy-supply = <&vdda_usb2_ss_1p2>;
 187         vdda-pll-supply = <&vdda_usb2_ss_core>;
 188
 189         usb3-phy@200 {
 190             reg = <0x200 0x128>,
 191                   <0x400 0x200>,
 192                   <0xc00 0x218>,
 193                   <0x600 0x128>,
 194                   <0x800 0x200>,
 195                   <0xa00 0x100>;
 196             #clock-cells = <0>;
 197             #phy-cells = <0>;
 198             clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
 199             clock-names = "pipe0";
 200             clock-output-names = "usb3_phy_pipe_clk_src";
 201         };
 202
 203         dp-phy@88ea200 {
 204             reg = <0xa200 0x200>,
 205                   <0xa400 0x200>,
 206                   <0xaa00 0x200>,
 207                   <0xa600 0x200>,
 208                   <0xa800 0x200>;
 209             #clock-cells = <1>;
 210             #phy-cells = <0>;
 211         };
 212     };