Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm QMP PHY controller (PCIe, IPQ8074)
   8
   9 maintainers:
  10   - Vinod Koul <vkoul@kernel.org>
  11
  12 description:
  13   QMP PHY controller supports physical layer functionality for a number of
  14   controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
  15
  16 properties:
  17   compatible:
  18     enum:
  19       - qcom,ipq6018-qmp-pcie-phy
  20       - qcom,ipq8074-qmp-gen3-pcie-phy
  21       - qcom,ipq8074-qmp-pcie-phy
  22
  23   reg:
  24     items:
  25       - description: serdes
  26
  27   clocks:
  28     maxItems: 3
  29
  30   clock-names:
  31     items:
  32       - const: aux
  33       - const: cfg_ahb
  34       - const: pipe
  35
  36   resets:
  37     maxItems: 2
  38
  39   reset-names:
  40     items:
  41       - const: phy
  42       - const: common
  43
  44   "#clock-cells":
  45     const: 0
  46
  47   clock-output-names:
  48     maxItems: 1
  49
  50   "#phy-cells":
  51     const: 0
  52
  53 required:
  54   - compatible
  55   - reg
  56   - clocks
  57   - clock-names
  58   - resets
  59   - reset-names
  60   - "#clock-cells"
  61   - clock-output-names
  62   - "#phy-cells"
  63
  64 additionalProperties: false
  65
  66 examples:
  67   - |
  68     #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
  69     #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
  70
  71     phy@84000 {
  72         compatible = "qcom,ipq6018-qmp-pcie-phy";
  73         reg = <0x00084000 0x1000>;
  74
  75         clocks = <&gcc GCC_PCIE0_AUX_CLK>,
  76                  <&gcc GCC_PCIE0_AHB_CLK>,
  77                  <&gcc GCC_PCIE0_PIPE_CLK>;
  78         clock-names = "aux",
  79                       "cfg_ahb",
  80                       "pipe";
  81
  82         clock-output-names = "gcc_pcie0_pipe_clk_src";
  83         #clock-cells = <0>;
  84
  85         #phy-cells = <0>;
  86
  87         resets = <&gcc GCC_PCIE0_PHY_BCR>,
  88                  <&gcc GCC_PCIE0PHY_PHY_BCR>;
  89         reset-names = "phy",
  90                       "common";
  91     };