1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USB2.0 phy with inno IP block
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3228-usb2phy
17 - rockchip,rk3308-usb2phy
18 - rockchip,rk3328-usb2phy
19 - rockchip,rk3366-usb2phy
20 - rockchip,rk3399-usb2phy
21 - rockchip,rv1108-usb2phy
28 The usb 480m output clock name.
41 Phandle of the usb 480m clock.
43 assigned-clock-parents:
45 Parent of the usb 480m clock.
46 Select between usb-phy output 480m and xin24m.
47 Refer to clk/clock-bindings.txt for generic clock consumer properties.
51 Phandle to the extcon device providing the cable state for the otg phy.
54 $ref: /schemas/types.yaml#/definitions/phandle
56 Phandle to the syscon managing the 'usb general register files'.
57 When set the driver will request its phandle as one companion-grf
58 for some special SoCs (e.g rv1108).
62 additionalProperties: false
69 description: host linestate interrupt
76 Phandle to a regulator that provides power to VBUS.
77 See ./phy-bindings.txt for details.
86 additionalProperties: false
107 Phandle to a regulator that provides power to VBUS.
108 See ./phy-bindings.txt for details.
123 additionalProperties: false
127 #include <dt-bindings/clock/rk3399-cru.h>
128 #include <dt-bindings/interrupt-controller/arm-gic.h>
129 #include <dt-bindings/interrupt-controller/irq.h>
130 u2phy0: usb2phy@e450 {
131 compatible = "rockchip,rk3399-usb2phy";
133 clocks = <&cru SCLK_USB2PHY0_REF>;
134 clock-names = "phyclk";
135 clock-output-names = "clk_usbphy0_480m";
138 u2phy0_host: host-port {
139 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
140 interrupt-names = "linestate";
144 u2phy0_otg: otg-port {
145 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
146 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
147 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
148 interrupt-names = "otg-bvalid", "otg-id", "linestate";