1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence Sierra PHY binding
10 This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
11 multiprotocol combinations including protocols such as PCIe, USB etc.
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
33 - description: Sierra PHY reset.
34 - description: Sierra APB reset. This is optional.
46 Offset of the Sierra PHY configuration registers.
56 - const: cmn_refclk_dig_div
57 - const: cmn_refclk1_dig_div
62 A boolean property whose presence indicates that the PHY registers will be
63 configured by hardware. If not present, all sub-node optional properties
70 Each group of PHY lanes with a single master lane should be represented as
71 a sub-node. Note that the actual configuration of each lane is determined
72 by hardware strapping, and must match the configuration specified here.
76 The master lane number. This is the lowest numbered lane in the lane group.
84 Contains list of resets, one per lane, to get all the link lanes out of reset.
91 Specifies the type of PHY for which the group of PHY lanes is used.
92 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
93 $ref: /schemas/types.yaml#/definitions/uint32
98 Number of lanes in this group. The group is made up of consecutive lanes.
99 $ref: /schemas/types.yaml#/definitions/uint32
108 additionalProperties: false
118 additionalProperties: false
122 #include <dt-bindings/phy/phy.h>
125 #address-cells = <2>;
128 sierra-phy@fd240000 {
129 compatible = "cdns,sierra-phy-t0";
130 reg = <0x0 0xfd240000 0x0 0x40000>;
131 resets = <&phyrst 0>, <&phyrst 1>;
132 reset-names = "sierra_reset", "sierra_apb";
133 clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>;
134 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
135 #address-cells = <1>;
139 resets = <&phyrst 2>;
140 cdns,num-lanes = <2>;
142 cdns,phy-type = <PHY_TYPE_PCIE>;
146 resets = <&phyrst 4>;
147 cdns,num-lanes = <1>;
149 cdns,phy-type = <PHY_TYPE_PCIE>;