1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2020 MediaTek
5 $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller Device Tree Bindings
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
34 u2 port2 0x1800 U2PHY_COM
60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
62 added on V2; the FMREG bank for slew rate calibration is not used anymore
67 pattern: "^t-phy@[0-9a-f]+$"
73 - mediatek,mt2701-tphy
74 - mediatek,mt7623-tphy
75 - mediatek,mt7622-tphy
76 - mediatek,mt8516-tphy
77 - const: mediatek,generic-tphy-v1
80 - mediatek,mt2712-tphy
81 - mediatek,mt7629-tphy
82 - mediatek,mt8183-tphy
83 - mediatek,mt8186-tphy
84 - mediatek,mt8192-tphy
85 - mediatek,mt8365-tphy
86 - const: mediatek,generic-tphy-v2
89 - mediatek,mt8188-tphy
90 - mediatek,mt8195-tphy
91 - const: mediatek,generic-tphy-v3
92 - const: mediatek,mt2701-u3phy
94 - const: mediatek,mt2712-u3phy
96 - const: mediatek,mt8173-u3phy
100 Register shared by multiple ports, exclude port's private register.
101 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
102 T-PHY V2/V3, such as mt2712.
111 # Used with non-empty value if optional 'reg' is not provided.
112 # The format of the value is an arbitrary number of triplets of
113 # (child-bus-address, parent-bus-address, length).
116 mediatek,src-ref-clk-mhz:
118 Frequency of reference clock for slew rate calibrate
123 Coefficient for slew rate calibrate, depends on SoC process
124 $ref: /schemas/types.yaml#/definitions/uint32
127 # Required child node:
129 "^(usb|pcie|sata)-phy@[0-9a-f]+$":
132 A sub-node is required for each port the controller provides.
133 Address range information including the usual 'reg' property
134 is used inside these nodes to describe the controller's topology.
143 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
144 - description: Reference clock of analog phy
146 Uses both clocks if the clock of analog and digital phys are
147 separated, otherwise uses "ref" clock only if needed.
158 The cells contain the following arguments.
160 - description: The PHY type
170 - description: internal R efuse for U2 PHY or U3/PCIe PHY
171 - description: rx_imp_sel efuse for U3/PCIe PHY
172 - description: tx_imp_sel efuse for U3/PCIe PHY
174 Phandles to nvmem cell that contains the efuse data;
175 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these
176 three items should be provided at the same time for U3/PCIe PHY,
177 when use software to load efuse;
178 If unspecified, will use hardware auto-load efuse.
186 # The following optional vendor properties are only for debug or HQA test
189 The value of slew rate calibrate (U2 phy)
190 $ref: /schemas/types.yaml#/definitions/uint32
196 The selection of VRT reference voltage (U2 phy)
197 $ref: /schemas/types.yaml#/definitions/uint32
203 The selection of HS_TX TERM reference voltage (U2 phy)
204 $ref: /schemas/types.yaml#/definitions/uint32
210 The selection of internal resistor (U2 phy)
211 $ref: /schemas/types.yaml#/definitions/uint32
217 The selection of disconnect threshold (U2 phy)
218 $ref: /schemas/types.yaml#/definitions/uint32
222 mediatek,pre-emphasis:
224 The level of pre-emphasis which used to widen the eye opening and
225 boost eye swing, the unit step is about 4.16% increment; e.g. the
226 level 1 means amplitude increases about 4.16%, the level 2 is about
228 $ref: /schemas/types.yaml#/definitions/uint32
234 Specify the flag to enable BC1.2 if support it
237 mediatek,syscon-type:
238 $ref: /schemas/types.yaml#/definitions/phandle-array
241 A phandle to syscon used to access the register of type switch,
242 the field should always be 3 cells long.
246 The first cell represents a phandle to syscon
248 The second cell represents the register offset
250 The third cell represents the index of config segment
257 additionalProperties: false
265 additionalProperties: false
269 #include <dt-bindings/clock/mt8173-clk.h>
270 #include <dt-bindings/interrupt-controller/arm-gic.h>
271 #include <dt-bindings/interrupt-controller/irq.h>
272 #include <dt-bindings/phy/phy.h>
274 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
275 reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
276 reg-names = "mac", "ippc";
277 phys = <&u2port0 PHY_TYPE_USB2>,
278 <&u3port0 PHY_TYPE_USB3>,
279 <&u2port1 PHY_TYPE_USB2>;
280 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
281 clocks = <&topckgen CLK_TOP_USB30_SEL>;
282 clock-names = "sys_ck";
286 compatible = "mediatek,mt8173-u3phy";
287 reg = <0x11290000 0x800>;
288 #address-cells = <1>;
292 u2port0: usb-phy@11290800 {
293 reg = <0x11290800 0x100>;
294 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>;
295 clock-names = "ref", "da_ref";
299 u3port0: usb-phy@11290900 {
300 reg = <0x11290900 0x700>;
306 u2port1: usb-phy@11291000 {
307 reg = <0x11291000 0x100>;