phy: samsung: Add support for the Exynos5420 variant of the USB2 PHY
[platform/kernel/linux-starfive.git] / Documentation / devicetree / bindings / phy / allwinner,sun5i-a13-usb-phy.yaml
1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun5i-a13-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Allwinner A13 USB PHY Device Tree Bindings
8
9 maintainers:
10   - Chen-Yu Tsai <wens@csie.org>
11   - Maxime Ripard <mripard@kernel.org>
12
13 properties:
14   "#phy-cells":
15     const: 1
16
17   compatible:
18     const: allwinner,sun5i-a13-usb-phy
19
20   reg:
21     items:
22       - description: PHY Control registers
23       - description: PHY PMU1 registers
24
25   reg-names:
26     items:
27       - const: phy_ctrl
28       - const: pmu1
29
30   clocks:
31     maxItems: 1
32     description: USB OTG PHY bus clock
33
34   clock-names:
35     const: usb_phy
36
37   resets:
38     items:
39       - description: USB OTG reset
40       - description: USB Host 1 Controller reset
41
42   reset-names:
43     items:
44       - const: usb0_reset
45       - const: usb1_reset
46
47   usb0_id_det-gpios:
48     description: GPIO to the USB OTG ID pin
49
50   usb0_vbus_det-gpios:
51     description: GPIO to the USB OTG VBUS detect pin
52
53   usb0_vbus_power-supply:
54     description: Power supply to detect the USB OTG VBUS
55
56   usb0_vbus-supply:
57     description: Regulator controlling USB OTG VBUS
58
59   usb1_vbus-supply:
60     description: Regulator controlling USB1 Host controller
61
62 required:
63   - "#phy-cells"
64   - compatible
65   - clocks
66   - clock-names
67   - reg
68   - reg-names
69   - resets
70   - reset-names
71
72 additionalProperties: false
73
74 examples:
75   - |
76     #include <dt-bindings/gpio/gpio.h>
77     #include <dt-bindings/clock/sun5i-ccu.h>
78     #include <dt-bindings/reset/sun5i-ccu.h>
79
80     phy@1c13400 {
81         #phy-cells = <1>;
82         compatible = "allwinner,sun5i-a13-usb-phy";
83         reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
84         reg-names = "phy_ctrl", "pmu1";
85         clocks = <&ccu CLK_USB_PHY0>;
86         clock-names = "usb_phy";
87         resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
88         reset-names = "usb0_reset", "usb1_reset";
89         usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
90         usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
91         usb0_vbus-supply = <&reg_usb0_vbus>;
92         usb1_vbus-supply = <&reg_usb1_vbus>;
93     };