1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PCI express root complex
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Stanimir Varbanov <svarbanov@mm-sol.com>
14 Qualcomm PCIe root complex controller is bansed on the Synopsys DesignWare
21 - qcom,pcie-ipq8064-v2
32 - qcom,pcie-sm8450-pcie0
33 - qcom,pcie-sm8450-pcie1
51 # Common definitions for clocks, clock-names and reset.
52 # Platform constraints are described later.
70 description: A phandle to the core analog power supply
73 description: A phandle to the core analog power supply for PHY
76 description: A phandle to the core analog power supply for IC which generates reference clock
79 description: A phandle to the PCIe endpoint power supply
92 description: GPIO controlled connection to PERST# signal
96 description: GPIO controlled connection to WAKE# signal
112 - $ref: /schemas/pci/pci-bus.yaml#
121 - qcom,pcie-ipq8064v2
131 - const: dbi # DesignWare PCIe registers
132 - const: elbi # External local bus interface registers
133 - const: parf # Qualcomm specific registers
134 - const: config # PCIe configuration space
149 - const: dbi # DesignWare PCIe registers
150 - const: elbi # External local bus interface registers
151 - const: atu # ATU address space
152 - const: parf # Qualcomm specific registers
153 - const: config # PCIe configuration space
170 - const: parf # Qualcomm specific registers
171 - const: dbi # DesignWare PCIe registers
172 - const: elbi # External local bus interface registers
173 - const: config # PCIe configuration space
182 - qcom,pcie-sm8450-pcie0
183 - qcom,pcie-sm8450-pcie1
191 - const: parf # Qualcomm specific registers
192 - const: dbi # DesignWare PCIe registers
193 - const: elbi # External local bus interface registers
194 - const: atu # ATU address space
195 - const: config # PCIe configuration space
204 - qcom,pcie-ipq8064v2
213 - const: core # Clocks the pcie hw block
214 - const: iface # Configuration AHB clock
215 - const: phy # Clocks the pcie PHY block
216 - const: aux # Clocks the pcie AUX block, not on apq8064
217 - const: ref # Clocks the pcie ref block, not on apq8064
224 - const: axi # AXI reset
225 - const: ahb # AHB reset
226 - const: por # POR reset
227 - const: pci # PCI reset
228 - const: phy # PHY reset
229 - const: ext # EXT reset, not on apq8064
248 - const: iface # Configuration AHB clock
249 - const: master_bus # Master AXI clock
250 - const: slave_bus # Slave AXI clock
251 - const: aux # Auxiliary (AUX) clock
256 - const: core # Core reset
271 - const: aux # Auxiliary (AUX) clock
272 - const: master_bus # Master AXI clock
273 - const: slave_bus # Slave AXI clock
279 - const: axi_m # AXI master reset
280 - const: axi_s # AXI slave reset
281 - const: pipe # PIPE reset
282 - const: axi_m_vmid # VMID reset
283 - const: axi_s_xpu # XPU reset
284 - const: parf # PARF reset
285 - const: phy # PHY reset
286 - const: axi_m_sticky # AXI sticky reset
287 - const: pipe_sticky # PIPE sticky reset
288 - const: pwr # PWR reset
289 - const: ahb # AHB reset
290 - const: phy_ahb # PHY AHB reset
303 - const: pipe # Pipe Clock driving internal logic
304 - const: aux # Auxiliary (AUX) clock
305 - const: cfg # Configuration clock
306 - const: bus_master # Master AXI clock
307 - const: bus_slave # Slave AXI clock
311 - const: pipe # Pipe Clock driving internal logic
312 - const: bus_master # Master AXI clock
313 - const: bus_slave # Slave AXI clock
314 - const: cfg # Configuration clock
315 - const: aux # Auxiliary (AUX) clock
336 - const: iface # PCIe to SysNOC BIU clock
337 - const: axi_m # AXI Master clock
338 - const: axi_s # AXI Slave clock
339 - const: ahb # AHB clock
340 - const: aux # Auxiliary clock
346 - const: pipe # PIPE reset
347 - const: sleep # Sleep reset
348 - const: sticky # Core Sticky reset
349 - const: axi_m # AXI Master reset
350 - const: axi_s # AXI Slave reset
351 - const: ahb # AHB Reset
352 - const: axi_m_sticky # AXI Master Sticky reset
367 - const: iface # PCIe to SysNOC BIU clock
368 - const: axi_m # AXI Master clock
369 - const: axi_s # AXI Slave clock
370 - const: axi_bridge # AXI bridge clock
377 - const: pipe # PIPE reset
378 - const: sleep # Sleep reset
379 - const: sticky # Core Sticky reset
380 - const: axi_m # AXI Master reset
381 - const: axi_s # AXI Slave reset
382 - const: ahb # AHB Reset
383 - const: axi_m_sticky # AXI Master Sticky reset
384 - const: axi_s_sticky # AXI Slave Sticky reset
399 - const: iface # AHB clock
400 - const: aux # Auxiliary clock
401 - const: master_bus # AXI Master clock
402 - const: slave_bus # AXI Slave clock
408 - const: axi_m # AXI Master reset
409 - const: axi_s # AXI Slave reset
410 - const: axi_m_sticky # AXI Master Sticky reset
411 - const: pipe_sticky # PIPE sticky reset
412 - const: pwr # PWR reset
413 - const: ahb # AHB reset
423 # Unfortunately the "optional" ref clock is used in the middle of the list
430 - const: pipe # PIPE clock
431 - const: aux # Auxiliary clock
432 - const: cfg # Configuration clock
433 - const: bus_master # Master AXI clock
434 - const: bus_slave # Slave AXI clock
435 - const: slave_q2a # Slave Q2A clock
436 - const: ref # REFERENCE clock
437 - const: tbu # PCIe TBU clock
444 - const: pipe # PIPE clock
445 - const: aux # Auxiliary clock
446 - const: cfg # Configuration clock
447 - const: bus_master # Master AXI clock
448 - const: bus_slave # Slave AXI clock
449 - const: slave_q2a # Slave Q2A clock
450 - const: tbu # PCIe TBU clock
456 - const: pci # PCIe core reset
468 # Unfortunately the "optional" ref clock is used in the middle of the list
475 - const: pipe # PIPE clock
476 - const: aux # Auxiliary clock
477 - const: cfg # Configuration clock
478 - const: bus_master # Master AXI clock
479 - const: bus_slave # Slave AXI clock
480 - const: slave_q2a # Slave Q2A clock
481 - const: ref # REFERENCE clock
482 - const: tbu # PCIe TBU clock
483 - const: ddrss_sf_tbu # PCIe SF TBU clock
490 - const: pipe # PIPE clock
491 - const: aux # Auxiliary clock
492 - const: cfg # Configuration clock
493 - const: bus_master # Master AXI clock
494 - const: bus_slave # Slave AXI clock
495 - const: slave_q2a # Slave Q2A clock
496 - const: tbu # PCIe TBU clock
497 - const: ddrss_sf_tbu # PCIe SF TBU clock
503 - const: pci # PCIe core reset
510 - qcom,pcie-sm8450-pcie0
518 - const: pipe # PIPE clock
519 - const: pipe_mux # PIPE MUX
520 - const: phy_pipe # PIPE output clock
521 - const: ref # REFERENCE clock
522 - const: aux # Auxiliary clock
523 - const: cfg # Configuration clock
524 - const: bus_master # Master AXI clock
525 - const: bus_slave # Slave AXI clock
526 - const: slave_q2a # Slave Q2A clock
527 - const: ddrss_sf_tbu # PCIe SF TBU clock
528 - const: aggre0 # Aggre NoC PCIe0 AXI clock
529 - const: aggre1 # Aggre NoC PCIe1 AXI clock
534 - const: pci # PCIe core reset
541 - qcom,pcie-sm8450-pcie1
549 - const: pipe # PIPE clock
550 - const: pipe_mux # PIPE MUX
551 - const: phy_pipe # PIPE output clock
552 - const: ref # REFERENCE clock
553 - const: aux # Auxiliary clock
554 - const: cfg # Configuration clock
555 - const: bus_master # Master AXI clock
556 - const: bus_slave # Slave AXI clock
557 - const: slave_q2a # Slave Q2A clock
558 - const: ddrss_sf_tbu # PCIe SF TBU clock
559 - const: aggre1 # Aggre NoC PCIe1 AXI clock
564 - const: pci # PCIe core reset
575 - qcom,pcie-ipq8064v2
594 unevaluatedProperties: false
598 #include <dt-bindings/interrupt-controller/arm-gic.h>
600 compatible = "qcom,pcie-ipq8064";
601 reg = <0x1b500000 0x1000>,
604 <0x0ff00000 0x100000>;
605 reg-names = "dbi", "elbi", "parf", "config";
607 linux,pci-domain = <0>;
608 bus-range = <0x00 0xff>;
610 #address-cells = <3>;
612 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
613 <0x82000000 0 0 0x08000000 0 0x07e00000>;
614 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
615 interrupt-names = "msi";
616 #interrupt-cells = <1>;
617 interrupt-map-mask = <0 0 0 0x7>;
618 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
619 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
620 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
621 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
627 clock-names = "core", "iface", "phy", "aux", "ref";
634 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
635 pinctrl-0 = <&pcie_pins_default>;
636 pinctrl-names = "default";
637 vdda-supply = <&pm8921_s3>;
638 vdda_phy-supply = <&pm8921_lvs6>;
639 vdda_refclk-supply = <&ext_3p3v>;
642 #include <dt-bindings/interrupt-controller/arm-gic.h>
643 #include <dt-bindings/gpio/gpio.h>
645 compatible = "qcom,pcie-apq8084";
646 reg = <0xfc520000 0x2000>,
650 reg-names = "parf", "dbi", "elbi", "config";
652 linux,pci-domain = <0>;
653 bus-range = <0x00 0xff>;
655 #address-cells = <3>;
657 ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
658 <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
659 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
660 interrupt-names = "msi";
661 #interrupt-cells = <1>;
662 interrupt-map-mask = <0 0 0 0x7>;
663 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
664 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
665 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
666 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
671 clock-names = "iface", "master_bus", "slave_bus", "aux";
673 reset-names = "core";
674 power-domains = <&gcc 1>;
675 vdda-supply = <&pma8084_l3>;
677 phy-names = "pciephy";
678 perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
679 pinctrl-0 = <&pcie0_pins_default>;
680 pinctrl-names = "default";