1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PCI express root complex
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Stanimir Varbanov <svarbanov@mm-sol.com>
14 Qualcomm PCIe root complex controller is bansed on the Synopsys DesignWare
21 - qcom,pcie-ipq8064-v2
33 - qcom,pcie-sm8450-pcie0
34 - qcom,pcie-sm8450-pcie1
52 # Common definitions for clocks, clock-names and reset.
53 # Platform constraints are described later.
71 description: A phandle to the core analog power supply
74 description: A phandle to the core analog power supply for PHY
77 description: A phandle to the core analog power supply for IC which generates reference clock
80 description: A phandle to the PCIe endpoint power supply
93 description: GPIO controlled connection to PERST# signal
97 description: GPIO controlled connection to WAKE# signal
113 - $ref: /schemas/pci/pci-bus.yaml#
122 - qcom,pcie-ipq8064v2
132 - const: dbi # DesignWare PCIe registers
133 - const: elbi # External local bus interface registers
134 - const: parf # Qualcomm specific registers
135 - const: config # PCIe configuration space
150 - const: dbi # DesignWare PCIe registers
151 - const: elbi # External local bus interface registers
152 - const: atu # ATU address space
153 - const: parf # Qualcomm specific registers
154 - const: config # PCIe configuration space
171 - const: parf # Qualcomm specific registers
172 - const: dbi # DesignWare PCIe registers
173 - const: elbi # External local bus interface registers
174 - const: config # PCIe configuration space
184 - qcom,pcie-sm8450-pcie0
185 - qcom,pcie-sm8450-pcie1
193 - const: parf # Qualcomm specific registers
194 - const: dbi # DesignWare PCIe registers
195 - const: elbi # External local bus interface registers
196 - const: atu # ATU address space
197 - const: config # PCIe configuration space
206 - qcom,pcie-ipq8064v2
215 - const: core # Clocks the pcie hw block
216 - const: iface # Configuration AHB clock
217 - const: phy # Clocks the pcie PHY block
218 - const: aux # Clocks the pcie AUX block, not on apq8064
219 - const: ref # Clocks the pcie ref block, not on apq8064
226 - const: axi # AXI reset
227 - const: ahb # AHB reset
228 - const: por # POR reset
229 - const: pci # PCI reset
230 - const: phy # PHY reset
231 - const: ext # EXT reset, not on apq8064
250 - const: iface # Configuration AHB clock
251 - const: master_bus # Master AXI clock
252 - const: slave_bus # Slave AXI clock
253 - const: aux # Auxiliary (AUX) clock
258 - const: core # Core reset
273 - const: aux # Auxiliary (AUX) clock
274 - const: master_bus # Master AXI clock
275 - const: slave_bus # Slave AXI clock
281 - const: axi_m # AXI master reset
282 - const: axi_s # AXI slave reset
283 - const: pipe # PIPE reset
284 - const: axi_m_vmid # VMID reset
285 - const: axi_s_xpu # XPU reset
286 - const: parf # PARF reset
287 - const: phy # PHY reset
288 - const: axi_m_sticky # AXI sticky reset
289 - const: pipe_sticky # PIPE sticky reset
290 - const: pwr # PWR reset
291 - const: ahb # AHB reset
292 - const: phy_ahb # PHY AHB reset
305 - const: pipe # Pipe Clock driving internal logic
306 - const: aux # Auxiliary (AUX) clock
307 - const: cfg # Configuration clock
308 - const: bus_master # Master AXI clock
309 - const: bus_slave # Slave AXI clock
313 - const: pipe # Pipe Clock driving internal logic
314 - const: bus_master # Master AXI clock
315 - const: bus_slave # Slave AXI clock
316 - const: cfg # Configuration clock
317 - const: aux # Auxiliary (AUX) clock
338 - const: iface # PCIe to SysNOC BIU clock
339 - const: axi_m # AXI Master clock
340 - const: axi_s # AXI Slave clock
341 - const: ahb # AHB clock
342 - const: aux # Auxiliary clock
348 - const: pipe # PIPE reset
349 - const: sleep # Sleep reset
350 - const: sticky # Core Sticky reset
351 - const: axi_m # AXI Master reset
352 - const: axi_s # AXI Slave reset
353 - const: ahb # AHB Reset
354 - const: axi_m_sticky # AXI Master Sticky reset
369 - const: iface # PCIe to SysNOC BIU clock
370 - const: axi_m # AXI Master clock
371 - const: axi_s # AXI Slave clock
372 - const: axi_bridge # AXI bridge clock
379 - const: pipe # PIPE reset
380 - const: sleep # Sleep reset
381 - const: sticky # Core Sticky reset
382 - const: axi_m # AXI Master reset
383 - const: axi_s # AXI Slave reset
384 - const: ahb # AHB Reset
385 - const: axi_m_sticky # AXI Master Sticky reset
386 - const: axi_s_sticky # AXI Slave Sticky reset
401 - const: iface # AHB clock
402 - const: aux # Auxiliary clock
403 - const: master_bus # AXI Master clock
404 - const: slave_bus # AXI Slave clock
410 - const: axi_m # AXI Master reset
411 - const: axi_s # AXI Slave reset
412 - const: axi_m_sticky # AXI Master Sticky reset
413 - const: pipe_sticky # PIPE sticky reset
414 - const: pwr # PWR reset
415 - const: ahb # AHB reset
430 - const: pipe # PIPE clock
431 - const: pipe_mux # PIPE MUX
432 - const: phy_pipe # PIPE output clock
433 - const: ref # REFERENCE clock
434 - const: aux # Auxiliary clock
435 - const: cfg # Configuration clock
436 - const: bus_master # Master AXI clock
437 - const: bus_slave # Slave AXI clock
438 - const: slave_q2a # Slave Q2A clock
439 - const: tbu # PCIe TBU clock
440 - const: ddrss_sf_tbu # PCIe SF TBU clock
445 - const: pci # PCIe core reset
455 # Unfortunately the "optional" ref clock is used in the middle of the list
462 - const: pipe # PIPE clock
463 - const: aux # Auxiliary clock
464 - const: cfg # Configuration clock
465 - const: bus_master # Master AXI clock
466 - const: bus_slave # Slave AXI clock
467 - const: slave_q2a # Slave Q2A clock
468 - const: ref # REFERENCE clock
469 - const: tbu # PCIe TBU clock
476 - const: pipe # PIPE clock
477 - const: aux # Auxiliary clock
478 - const: cfg # Configuration clock
479 - const: bus_master # Master AXI clock
480 - const: bus_slave # Slave AXI clock
481 - const: slave_q2a # Slave Q2A clock
482 - const: tbu # PCIe TBU clock
488 - const: pci # PCIe core reset
500 # Unfortunately the "optional" ref clock is used in the middle of the list
507 - const: pipe # PIPE clock
508 - const: aux # Auxiliary clock
509 - const: cfg # Configuration clock
510 - const: bus_master # Master AXI clock
511 - const: bus_slave # Slave AXI clock
512 - const: slave_q2a # Slave Q2A clock
513 - const: ref # REFERENCE clock
514 - const: tbu # PCIe TBU clock
515 - const: ddrss_sf_tbu # PCIe SF TBU clock
522 - const: pipe # PIPE clock
523 - const: aux # Auxiliary clock
524 - const: cfg # Configuration clock
525 - const: bus_master # Master AXI clock
526 - const: bus_slave # Slave AXI clock
527 - const: slave_q2a # Slave Q2A clock
528 - const: tbu # PCIe TBU clock
529 - const: ddrss_sf_tbu # PCIe SF TBU clock
535 - const: pci # PCIe core reset
542 - qcom,pcie-sm8450-pcie0
550 - const: pipe # PIPE clock
551 - const: pipe_mux # PIPE MUX
552 - const: phy_pipe # PIPE output clock
553 - const: ref # REFERENCE clock
554 - const: aux # Auxiliary clock
555 - const: cfg # Configuration clock
556 - const: bus_master # Master AXI clock
557 - const: bus_slave # Slave AXI clock
558 - const: slave_q2a # Slave Q2A clock
559 - const: ddrss_sf_tbu # PCIe SF TBU clock
560 - const: aggre0 # Aggre NoC PCIe0 AXI clock
561 - const: aggre1 # Aggre NoC PCIe1 AXI clock
566 - const: pci # PCIe core reset
573 - qcom,pcie-sm8450-pcie1
581 - const: pipe # PIPE clock
582 - const: pipe_mux # PIPE MUX
583 - const: phy_pipe # PIPE output clock
584 - const: ref # REFERENCE clock
585 - const: aux # Auxiliary clock
586 - const: cfg # Configuration clock
587 - const: bus_master # Master AXI clock
588 - const: bus_slave # Slave AXI clock
589 - const: slave_q2a # Slave Q2A clock
590 - const: ddrss_sf_tbu # PCIe SF TBU clock
591 - const: aggre1 # Aggre NoC PCIe1 AXI clock
596 - const: pci # PCIe core reset
607 - qcom,pcie-ipq8064v2
626 unevaluatedProperties: false
630 #include <dt-bindings/interrupt-controller/arm-gic.h>
632 compatible = "qcom,pcie-ipq8064";
633 reg = <0x1b500000 0x1000>,
636 <0x0ff00000 0x100000>;
637 reg-names = "dbi", "elbi", "parf", "config";
639 linux,pci-domain = <0>;
640 bus-range = <0x00 0xff>;
642 #address-cells = <3>;
644 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
645 <0x82000000 0 0 0x08000000 0 0x07e00000>;
646 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
647 interrupt-names = "msi";
648 #interrupt-cells = <1>;
649 interrupt-map-mask = <0 0 0 0x7>;
650 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
651 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
652 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
653 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
659 clock-names = "core", "iface", "phy", "aux", "ref";
666 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
667 pinctrl-0 = <&pcie_pins_default>;
668 pinctrl-names = "default";
669 vdda-supply = <&pm8921_s3>;
670 vdda_phy-supply = <&pm8921_lvs6>;
671 vdda_refclk-supply = <&ext_3p3v>;
674 #include <dt-bindings/interrupt-controller/arm-gic.h>
675 #include <dt-bindings/gpio/gpio.h>
677 compatible = "qcom,pcie-apq8084";
678 reg = <0xfc520000 0x2000>,
682 reg-names = "parf", "dbi", "elbi", "config";
684 linux,pci-domain = <0>;
685 bus-range = <0x00 0xff>;
687 #address-cells = <3>;
689 ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
690 <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
691 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
692 interrupt-names = "msi";
693 #interrupt-cells = <1>;
694 interrupt-map-mask = <0 0 0 0x7>;
695 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
696 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
697 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
698 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
703 clock-names = "iface", "master_bus", "slave_bus", "aux";
705 reset-names = "core";
706 power-domains = <&gcc 1>;
707 vdda-supply = <&pma8084_l3>;
709 phy-names = "pciephy";
710 perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
711 pinctrl-0 = <&pcie0_pins_default>;
712 pinctrl-names = "default";