1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom iProc PCIe controller with the platform bus interface
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-bus.yaml#
15 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
21 # for the first generation of PAXB based controller, used in SoCs
22 # including NSP, Cygnus, NS2, and Pegasus
24 # for the second generation of PAXB-based controllers, used in
26 - brcm,iproc-pcie-paxb-v2
27 # For the first generation of PAXC based controller, used in NS2
28 - brcm,iproc-pcie-paxc
29 # For the second generation of PAXC based controller, used in Stingray
30 - brcm,iproc-pcie-paxc-v2
35 Base address and length of the PCIe controller I/O register space
39 interrupt-map-mask: true
48 Ranges for the PCI memory and I/O regions
61 "#address-cells": true
70 Some iProc SoCs do not have the outbound address mapping done by the
71 ASIC after power on reset. In this case, SW needs to configure it
73 brcm,pcie-ob-axi-offset:
74 $ref: /schemas/types.yaml#/definitions/uint32
76 The offset from the AXI address to the internal address used by the
77 iProc PCIe core (not the PCIe address)
84 - const: brcm,iproc-msi
93 Needs to be present for some older iProc platforms that require the
94 interrupt enable registers to be set explicitly to enable MSI
97 brcm,pcie-ob-axi-offset: ["brcm,pcie-ob"]
98 brcm,pcie-msi-inten: [msi-controller]
116 unevaluatedProperties: false
120 #include <dt-bindings/interrupt-controller/arm-gic.h>
123 #address-cells = <1>;
125 pcie0: pcie@18012000 {
126 compatible = "brcm,iproc-pcie";
127 reg = <0x18012000 0x1000>;
129 #interrupt-cells = <1>;
130 interrupt-map-mask = <0 0 0 0>;
131 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
133 linux,pci-domain = <0>;
135 bus-range = <0x00 0xff>;
137 #address-cells = <3>;
140 ranges = <0x81000000 0 0 0x28000000 0 0x00010000>,
141 <0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
144 phy-names = "pcie-phy";
147 brcm,pcie-ob-axi-offset = <0x00000000>;
149 msi-parent = <&msi0>;
151 /* iProc event queue based MSI */
153 compatible = "brcm,iproc-msi";
155 interrupt-parent = <&gic>;
156 interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
157 <GIC_SPI 97 IRQ_TYPE_NONE>,
158 <GIC_SPI 98 IRQ_TYPE_NONE>,
159 <GIC_SPI 99 IRQ_TYPE_NONE>;
163 pcie1: pcie@18013000 {
164 compatible = "brcm,iproc-pcie";
165 reg = <0x18013000 0x1000>;
167 #interrupt-cells = <1>;
168 interrupt-map-mask = <0 0 0 0>;
169 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
171 linux,pci-domain = <1>;
173 bus-range = <0x00 0xff>;
175 #address-cells = <3>;
178 ranges = <0x81000000 0 0 0x48000000 0 0x00010000>,
179 <0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
182 phy-names = "pcie-phy";