1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The TI AM654x/J721E SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
15 (one external) and provides Ethernet packet communication for the device.
16 CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII),
17 Reduced Media Independent Interface (RMII), the Management Data
18 Input/Output (MDIO) interface for physical layer device (PHY) management,
19 new version of Common Platform Time Sync (CPTS), updated Address Lookup
21 One external Ethernet port (port 1) with selectable RGMII/RMII interfaces and
22 an internal Communications Port Programming Interface (CPPI5) (Host port 0).
23 Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
24 and one RX channels and operating by TI AM654x/J721E NAVSS Unified DMA
25 Peripheral Root Complex (UDMA-P) controller.
26 The CPSW2G NUSS is integrated into device MCU domain named MCU_CPSW0.
29 priority level Quality Of Service (QOS) support (802.1p)
30 Support for Audio/Video Bridging (P802.1Qav/D6.0)
31 Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
32 Flow Control (802.3x) Support
33 Time Sensitive Network Support
34 IEEE P902.3br/D2.0 Interspersing Express Traffic
35 IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
36 Configurable number of addresses plus VLANs
37 Configurable number of classifier/policers
38 VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
39 ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
42 Specifications can be found at
43 http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
44 http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf
47 "#address-cells": true
52 - const: ti,am654-cpsw-nuss
53 - const: ti,j721e-cpsw-nuss
58 The physical base address and size of full the CPSW2G NUSS IO range
69 description: CPSW2G NUSS functional clock
104 description: CPSW2G NUSS external ports
107 - $ref: ethernet-controller.yaml#
113 description: CPSW port number
117 description: phandle on phy-gmii-sel PHY
120 description: label associated with this port
123 $ref: /schemas/types.yaml#definitions/flag
125 Specifies the port works in mac-only mode.
128 $ref: /schemas/types.yaml#definitions/phandle-array
130 Phandle to the system control device node which provides access
131 to efuse IO range with MAC addresses
137 additionalProperties: false
143 - $ref: "ti,davinci-mdio.yaml#"
150 - $ref: "ti,k3-am654-cpts.yaml#"
152 CPSW Common Platform Time Sync (CPTS) module.
167 additionalProperties: false
171 #include <dt-bindings/pinctrl/k3.h>
172 #include <dt-bindings/soc/ti,sci_pm_domain.h>
173 #include <dt-bindings/net/ti-dp83867.h>
175 mcu_cpsw: ethernet@46000000 {
176 compatible = "ti,am654-cpsw-nuss";
177 #address-cells = <2>;
179 reg = <0x0 0x46000000 0x0 0x200000>;
180 reg-names = "cpsw_nuss";
181 ranges = <0x0 0x0 0x46000000 0x0 0x200000>;
183 clocks = <&k3_clks 5 10>;
185 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
189 dmas = <&mcu_udmap 0xf000>,
198 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
202 #address-cells = <1>;
209 ti,syscon-efuse = <&mcu_conf 0x200>;
210 phys = <&phy_gmii_sel 1>;
212 phy-mode = "rgmii-rxid";
213 phy-handle = <&phy0>;
217 davinci_mdio: mdio@f00 {
218 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
219 reg = <0x0 0xf00 0x0 0x100>;
220 #address-cells = <1>;
222 clocks = <&k3_clks 5 10>;
224 bus_freq = <1000000>;
226 phy0: ethernet-phy@0 {
228 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
229 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;