Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: TI SoC Ethernet Switch Controller (CPSW) Device Tree Bindings
   8
   9 maintainers:
  10   - Grygorii Strashko <grygorii.strashko@ti.com>
  11   - Sekhar Nori <nsekhar@ti.com>
  12
  13 description:
  14   The 3-port switch gigabit ethernet subsystem provides ethernet packet
  15   communication and can be configured as an ethernet switch. It provides the
  16   gigabit media independent interface (GMII),reduced gigabit media
  17   independent interface (RGMII), reduced media independent interface (RMII),
  18   the management data input output (MDIO) for physical layer device (PHY)
  19   management.
  20
  21 properties:
  22   compatible:
  23     oneOf:
  24       - const: ti,cpsw-switch
  25       - items:
  26          - const: ti,am335x-cpsw-switch
  27          - const: ti,cpsw-switch
  28       - items:
  29         - const: ti,am4372-cpsw-switch
  30         - const: ti,cpsw-switch
  31       - items:
  32         - const: ti,dra7-cpsw-switch
  33         - const: ti,cpsw-switch
  34
  35   reg:
  36     maxItems: 1
  37     description:
  38        The physical base address and size of full the CPSW module IO range
  39
  40   ranges: true
  41
  42   clocks:
  43     maxItems: 1
  44     description: CPSW functional clock
  45
  46   clock-names:
  47     maxItems: 1
  48     items:
  49       - const: fck
  50
  51   interrupts:
  52     items:
  53       - description: RX_THRESH interrupt
  54       - description: RX interrupt
  55       - description: TX interrupt
  56       - description: MISC interrupt
  57
  58   interrupt-names:
  59     items:
  60       - const: "rx_thresh"
  61       - const: "rx"
  62       - const: "tx"
  63       - const: "misc"
  64
  65   pinctrl-names: true
  66
  67   syscon:
  68     $ref: /schemas/types.yaml#definitions/phandle
  69     description:
  70       Phandle to the system control device node which provides access to
  71       efuse IO range with MAC addresses
  72
  73
  74   ethernet-ports:
  75     type: object
  76     properties:
  77       '#address-cells':
  78         const: 1
  79       '#size-cells':
  80         const: 0
  81
  82     patternProperties:
  83       "^port@[0-9]+$":
  84           type: object
  85           minItems: 1
  86           maxItems: 2
  87           description: CPSW external ports
  88
  89           allOf:
  90             - $ref: ethernet-controller.yaml#
  91
  92           properties:
  93             reg:
  94               maxItems: 1
  95               enum: [1, 2]
  96               description: CPSW port number
  97
  98             phys:
  99               $ref: /schemas/types.yaml#definitions/phandle-array
 100               maxItems: 1
 101               description:  phandle on phy-gmii-sel PHY
 102
 103             label:
 104               $ref: /schemas/types.yaml#/definitions/string-array
 105               maxItems: 1
 106               description: label associated with this port
 107
 108             ti,dual-emac-pvid:
 109               $ref: /schemas/types.yaml#/definitions/uint32
 110               maxItems: 1
 111               minimum: 1
 112               maximum: 1024
 113               description:
 114                 Specifies default PORT VID to be used to segregate
 115                 ports. Default value - CPSW port number.
 116
 117           required:
 118             - reg
 119             - phys
 120
 121   mdio:
 122     type: object
 123     allOf:
 124       - $ref: "ti,davinci-mdio.yaml#"
 125     description:
 126       CPSW MDIO bus.
 127
 128   cpts:
 129     type: object
 130     description:
 131       The Common Platform Time Sync (CPTS) module
 132
 133     properties:
 134       clocks:
 135         maxItems: 1
 136         description: CPTS reference clock
 137
 138       clock-names:
 139         maxItems: 1
 140         items:
 141           - const: cpts
 142
 143       cpts_clock_mult:
 144         $ref: /schemas/types.yaml#/definitions/uint32
 145         description:
 146           Numerator to convert input clock ticks into ns
 147
 148       cpts_clock_shift:
 149         $ref: /schemas/types.yaml#/definitions/uint32
 150         description:
 151           Denominator to convert input clock ticks into ns.
 152           Mult and shift will be calculated basing on CPTS rftclk frequency if
 153           both cpts_clock_shift and cpts_clock_mult properties are not provided.
 154
 155     required:
 156       - clocks
 157       - clock-names
 158
 159 required:
 160   - compatible
 161   - reg
 162   - ranges
 163   - clocks
 164   - clock-names
 165   - interrupts
 166   - interrupt-names
 167   - '#address-cells'
 168   - '#size-cells'
 169
 170 examples:
 171   - |
 172     #include <dt-bindings/interrupt-controller/irq.h>
 173     #include <dt-bindings/interrupt-controller/arm-gic.h>
 174     #include <dt-bindings/clock/dra7.h>
 175
 176     mac_sw: switch@0 {
 177         compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
 178         reg = <0x0 0x4000>;
 179         ranges = <0 0 0x4000>;
 180         clocks = <&gmac_main_clk>;
 181         clock-names = "fck";
 182         #address-cells = <1>;
 183         #size-cells = <1>;
 184         syscon = <&scm_conf>;
 185         inctrl-names = "default", "sleep";
 186
 187         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 188                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
 189                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
 190                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
 191         interrupt-names = "rx_thresh", "rx", "tx", "misc";
 192
 193         ethernet-ports {
 194                 #address-cells = <1>;
 195                 #size-cells = <0>;
 196
 197                 cpsw_port1: port@1 {
 198                         reg = <1>;
 199                         label = "port1";
 200                         mac-address = [ 00 00 00 00 00 00 ];
 201                         phys = <&phy_gmii_sel 1>;
 202                         phy-handle = <&ethphy0_sw>;
 203                         phy-mode = "rgmii";
 204                         ti,dual_emac_pvid = <1>;
 205                 };
 206
 207                 cpsw_port2: port@2 {
 208                         reg = <2>;
 209                         label = "wan";
 210                         mac-address = [ 00 00 00 00 00 00 ];
 211                         phys = <&phy_gmii_sel 2>;
 212                         phy-handle = <&ethphy1_sw>;
 213                         phy-mode = "rgmii";
 214                         ti,dual_emac_pvid = <2>;
 215                 };
 216         };
 217
 218         davinci_mdio_sw: mdio@1000 {
 219                 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 220                 reg = <0x1000 0x100>;
 221                 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
 222                 clock-names = "fck";
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 bus_freq = <1000000>;
 226
 227                 ethphy0_sw: ethernet-phy@0 {
 228                         reg = <0>;
 229                 };
 230
 231                 ethphy1_sw: ethernet-phy@1 {
 232                         reg = <1>;
 233                 };
 234         };
 235
 236         cpts {
 237                 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
 238                 clock-names = "cpts";
 239         };
 240     };