Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 # Copyright (C) 2022 StarFive Technology Co., Ltd.
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: StarFive JH7110 DWMAC glue layer
   9
  10 maintainers:
  11   - Emil Renner Berthing <kernel@esmil.dk>
  12   - Samin Guo <samin.guo@starfivetech.com>
  13
  14 select:
  15   properties:
  16     compatible:
  17       contains:
  18         enum:
  19           - starfive,jh7110-dwmac
  20   required:
  21     - compatible
  22
  23 properties:
  24   compatible:
  25     items:
  26       - enum:
  27           - starfive,jh7110-dwmac
  28       - const: snps,dwmac-5.20
  29
  30   clocks:
  31     items:
  32       - description: GMAC main clock
  33       - description: GMAC AHB clock
  34       - description: PTP clock
  35       - description: TX clock
  36       - description: GTX clock
  37
  38   clock-names:
  39     items:
  40       - const: stmmaceth
  41       - const: pclk
  42       - const: ptp_ref
  43       - const: tx
  44       - const: gtx
  45
  46   resets:
  47     items:
  48       - description: MAC Reset signal.
  49       - description: AHB Reset signal.
  50
  51   reset-names:
  52     items:
  53       - const: stmmaceth
  54       - const: ahb
  55
  56   starfive,tx-use-rgmii-clk:
  57     description:
  58       Tx clock is provided by external rgmii clock.
  59     type: boolean
  60
  61   starfive,syscon:
  62     $ref: /schemas/types.yaml#/definitions/phandle-array
  63     items:
  64       - items:
  65           - description: phandle to syscon that configures phy mode
  66           - description: Offset of phy mode selection
  67           - description: Shift of phy mode selection
  68     description:
  69       A phandle to syscon with two arguments that configure phy mode.
  70       The argument one is the offset of phy mode selection, the
  71       argument two is the shift of phy mode selection.
  72
  73 allOf:
  74   - $ref: snps,dwmac.yaml#
  75
  76 unevaluatedProperties: false
  77
  78 required:
  79   - compatible
  80   - clocks
  81   - clock-names
  82   - resets
  83   - reset-names
  84
  85 examples:
  86   - |
  87     ethernet@16030000 {
  88         compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
  89         reg = <0x16030000 0x10000>;
  90         clocks = <&clk 3>, <&clk 2>, <&clk 109>,
  91                  <&clk 6>, <&clk 111>;
  92         clock-names = "stmmaceth", "pclk", "ptp_ref",
  93                       "tx", "gtx";
  94         resets = <&rst 1>, <&rst 2>;
  95         reset-names = "stmmaceth", "ahb";
  96         interrupts = <7>, <6>, <5>;
  97         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
  98         phy-mode = "rgmii-id";
  99         snps,multicast-filter-bins = <64>;
 100         snps,perfect-filter-entries = <8>;
 101         rx-fifo-depth = <2048>;
 102         tx-fifo-depth = <2048>;
 103         snps,fixed-burst;
 104         snps,no-pbl-x8;
 105         snps,tso;
 106         snps,force_thresh_dma_mode;
 107         snps,axi-config = <&stmmac_axi_setup>;
 108         snps,en-tx-lpi-clockgating;
 109         snps,txpbl = <16>;
 110         snps,rxpbl = <16>;
 111         starfive,syscon = <&aon_syscon 0xc 0x12>;
 112         phy-handle = <&phy0>;
 113
 114         mdio {
 115             #address-cells = <1>;
 116             #size-cells = <0>;
 117             compatible = "snps,dwmac-mdio";
 118
 119             phy0: ethernet-phy@0 {
 120                 reg = <0>;
 121             };
 122         };
 123
 124         stmmac_axi_setup: stmmac-axi-config {
 125             snps,lpi_en;
 126             snps,wr_osr_lmt = <4>;
 127             snps,rd_osr_lmt = <4>;
 128             snps,blen = <256 128 64 32 0 0 0>;
 129         };
 130     };