1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022 StarFive Technology Co., Ltd.
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: StarFive JH7110 DWMAC glue layer
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7110-dwmac
27 - starfive,jh7110-dwmac
28 - const: snps,dwmac-5.20
32 - description: GMAC main clock
33 - description: GMAC AHB clock
34 - description: PTP clock
35 - description: TX clock
36 - description: GTX clock
48 - description: MAC Reset signal.
49 - description: AHB Reset signal.
56 starfive,tx-use-rgmii-clk:
58 Tx clock is provided by external rgmii clock.
62 $ref: /schemas/types.yaml#/definitions/phandle-array
65 - description: phandle to syscon that configures phy mode
66 - description: Offset of phy mode selection
67 - description: Shift of phy mode selection
69 A phandle to syscon with two arguments that configure phy mode.
70 The argument one is the offset of phy mode selection, the
71 argument two is the shift of phy mode selection.
74 - $ref: snps,dwmac.yaml#
76 unevaluatedProperties: false
88 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
89 reg = <0x16030000 0x10000>;
90 clocks = <&clk 3>, <&clk 2>, <&clk 109>,
92 clock-names = "stmmaceth", "pclk", "ptp_ref",
94 resets = <&rst 1>, <&rst 2>;
95 reset-names = "stmmaceth", "ahb";
96 interrupts = <7>, <6>, <5>;
97 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
98 phy-mode = "rgmii-id";
99 snps,multicast-filter-bins = <64>;
100 snps,perfect-filter-entries = <8>;
101 rx-fifo-depth = <2048>;
102 tx-fifo-depth = <2048>;
106 snps,force_thresh_dma_mode;
107 snps,axi-config = <&stmmac_axi_setup>;
108 snps,en-tx-lpi-clockgating;
111 starfive,syscon = <&aon_syscon 0xc 0x12>;
112 phy-handle = <&phy0>;
115 #address-cells = <1>;
117 compatible = "snps,dwmac-mdio";
119 phy0: ethernet-phy@0 {
124 stmmac_axi_setup: stmmac-axi-config {
126 snps,wr_osr_lmt = <4>;
127 snps,rd_osr_lmt = <4>;
128 snps,blen = <256 128 64 32 0 0 0>;