1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare MAC
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
14 # Select every compatible, including the deprecated ones. This way, we
15 # will be able to report a warning when we have that compatible, since
16 # we will validate the node thanks to the select, but won't report it
17 # as a valid value in the compatible property description
45 # We need to include all the compatibles from schemas that will
46 # include that schemas, otherwise compatible won't validate for
51 - allwinner,sun7i-a20-gmac
52 - allwinner,sun8i-a83t-emac
53 - allwinner,sun8i-h3-emac
54 - allwinner,sun8i-r40-gmac
55 - allwinner,sun8i-v3s-emac
56 - allwinner,sun50i-a64-emac
57 - amlogic,meson6-dwmac
58 - amlogic,meson8b-dwmac
59 - amlogic,meson8m2-dwmac
60 - amlogic,meson-gxbb-dwmac
61 - amlogic,meson-axg-dwmac
69 - renesas,r9a06g032-gmac
72 - rockchip,rk3128-gmac
73 - rockchip,rk3228-gmac
74 - rockchip,rk3288-gmac
75 - rockchip,rk3328-gmac
76 - rockchip,rk3366-gmac
77 - rockchip,rk3368-gmac
78 - rockchip,rk3588-gmac
79 - rockchip,rk3399-gmac
80 - rockchip,rv1108-gmac
102 - description: Combined signal for various interrupt events
103 - description: The interrupt to manage the remote wake-up packet detection
104 - description: The interrupt that occurs when Rx exits the LPI state
110 - const: eth_wake_irq
116 additionalItems: true
118 - description: GMAC main clock
119 - description: Peripheral registers interface clock
121 PTP reference clock. This clock is used for programming the
122 Timestamp Addend Register. If not passed then the system
123 clock will be used and this is fine on some platforms.
128 additionalItems: true
138 - description: GMAC stmmaceth reset
139 - description: AHB reset
151 $ref: ethernet-controller.yaml#/properties/phy-connection-type
153 The property is identical to 'phy-mode', and assumes that there is mode
154 converter in-between the MAC & PHY (e.g. GMII-to-RGMII). This converter
155 can be passive (no SW requirement), and requires that the MAC operate
156 in a different mode than the PHY in order to function.
159 $ref: /schemas/types.yaml#/definitions/phandle
161 AXI BUS Mode parameters. Phandle to a node that can contain the
163 * snps,lpi_en, enable Low Power Interface
164 * snps,xit_frm, unlock on WoL
165 * snps,wr_osr_lmt, max write outstanding req. limit
166 * snps,rd_osr_lmt, max read outstanding req. limit
167 * snps,kbbe, do not cross 1KiB boundary.
168 * snps,blen, this is a vector of supported burst length.
169 * snps,fb, fixed-burst
170 * snps,mb, mixed-burst
171 * snps,rb, rebuild INCRx Burst
174 $ref: /schemas/types.yaml#/definitions/phandle
176 Multiple RX Queues parameters. Phandle to a node that can
177 contain the following properties
178 * snps,rx-queues-to-use, number of RX queues to be used in the
180 * Choose one of these RX scheduling algorithms
181 * snps,rx-sched-sp, Strict priority
182 * snps,rx-sched-wsp, Weighted Strict priority
184 * Choose one of these modes
185 * snps,dcb-algorithm, Queue to be enabled as DCB
186 * snps,avb-algorithm, Queue to be enabled as AVB
187 * snps,map-to-dma-channel, Channel to map
188 * Specifiy specific packet routing
189 * snps,route-avcp, AV Untagged Control packets
190 * snps,route-ptp, PTP Packets
191 * snps,route-dcbcp, DCB Control Packets
192 * snps,route-up, Untagged Packets
193 * snps,route-multi-broad, Multicast & Broadcast Packets
194 * snps,priority, bitmask of the tagged frames priorities assigned to
198 $ref: /schemas/types.yaml#/definitions/phandle
200 Multiple TX Queues parameters. Phandle to a node that can
201 contain the following properties
202 * snps,tx-queues-to-use, number of TX queues to be used in the
204 * Choose one of these TX scheduling algorithms
205 * snps,tx-sched-wrr, Weighted Round Robin
206 * snps,tx-sched-wfq, Weighted Fair Queuing
207 * snps,tx-sched-dwrr, Deficit Weighted Round Robin
208 * snps,tx-sched-sp, Strict priority
210 * snps,weight, TX queue weight (if using a DCB weight
212 * Choose one of these modes
213 * snps,dcb-algorithm, TX queue will be working in DCB
214 * snps,avb-algorithm, TX queue will be working in AVB
215 [Attention] Queue 0 is reserved for legacy traffic
216 and so no AVB is available in this queue.
217 * Configure Credit Base Shaper (if AVB Mode selected)
218 * snps,send_slope, enable Low Power Interface
219 * snps,idle_slope, unlock on WoL
220 * snps,high_credit, max write outstanding req. limit
221 * snps,low_credit, max read outstanding req. limit
222 * snps,priority, bitmask of the priorities assigned to the queue.
223 When a PFC frame is received with priorities matching the bitmask,
224 the queue is blocked from transmitting for the pause time specified
233 snps,reset-active-low:
235 $ref: /schemas/types.yaml#/definitions/flag
237 Indicates that the PHY Reset is active low
239 snps,reset-delays-us:
242 Triplet of delays. The 1st cell is reset pre-delay in micro
243 seconds. The 2nd cell is reset pulse in micro seconds. The 3rd
244 cell is reset post-delay in micro seconds.
249 $ref: /schemas/types.yaml#/definitions/flag
251 Use Address-Aligned Beats
254 $ref: /schemas/types.yaml#/definitions/flag
256 Program the DMA to use the fixed burst mode
259 $ref: /schemas/types.yaml#/definitions/flag
261 Program the DMA to use the mixed burst mode
263 snps,force_thresh_dma_mode:
264 $ref: /schemas/types.yaml#/definitions/flag
266 Force DMA to use the threshold mode for both tx and rx
268 snps,force_sf_dma_mode:
269 $ref: /schemas/types.yaml#/definitions/flag
271 Force DMA to use the Store and Forward mode for both tx and
272 rx. This flag is ignored if force_thresh_dma_mode is set.
274 snps,en-tx-lpi-clockgating:
275 $ref: /schemas/types.yaml#/definitions/flag
277 Enable gating of the MAC TX clock during TX low-power mode
279 snps,multicast-filter-bins:
280 $ref: /schemas/types.yaml#/definitions/uint32
282 Number of multicast filter hash bins supported by this device
285 snps,perfect-filter-entries:
286 $ref: /schemas/types.yaml#/definitions/uint32
288 Number of perfect filter entries supported by this device
292 $ref: /schemas/types.yaml#/definitions/uint32
294 Port selection speed that can be passed to the core when PCS
295 is supported. For example, this is used in case of SGMII and
299 $ref: /schemas/types.yaml#/definitions/uint32
301 Frequency division factor for MDC clock.
305 unevaluatedProperties: false
307 Creates and registers an MDIO bus.
311 const: snps,dwmac-mdio
318 unevaluatedProperties: false
320 AXI BUS Mode parameters.
324 $ref: /schemas/types.yaml#/definitions/flag
326 enable Low Power Interface
329 $ref: /schemas/types.yaml#/definitions/flag
334 $ref: /schemas/types.yaml#/definitions/uint32
336 max write outstanding req. limit
339 $ref: /schemas/types.yaml#/definitions/uint32
341 max read outstanding req. limit
344 $ref: /schemas/types.yaml#/definitions/uint32
346 do not cross 1KiB boundary.
349 $ref: /schemas/types.yaml#/definitions/uint32-array
351 this is a vector of supported burst length.
356 $ref: /schemas/types.yaml#/definitions/flag
361 $ref: /schemas/types.yaml#/definitions/flag
366 $ref: /schemas/types.yaml#/definitions/flag
378 snps,reset-active-low: ["snps,reset-gpio"]
379 snps,reset-delay-us: ["snps,reset-gpio"]
382 - $ref: "ethernet-controller.yaml#"
388 - allwinner,sun7i-a20-gmac
389 - allwinner,sun8i-a83t-emac
390 - allwinner,sun8i-h3-emac
391 - allwinner,sun8i-r40-gmac
392 - allwinner,sun8i-v3s-emac
393 - allwinner,sun50i-a64-emac
411 Programmable Burst Length (tx and rx)
412 $ref: /schemas/types.yaml#/definitions/uint32
413 enum: [1, 2, 4, 8, 16, 32]
417 Tx Programmable Burst Length. If set, DMA tx will use this
418 value rather than snps,pbl.
419 $ref: /schemas/types.yaml#/definitions/uint32
420 enum: [1, 2, 4, 8, 16, 32]
424 Rx Programmable Burst Length. If set, DMA rx will use this
425 value rather than snps,pbl.
426 $ref: /schemas/types.yaml#/definitions/uint32
427 enum: [1, 2, 4, 8, 16, 32]
430 $ref: /schemas/types.yaml#/definitions/flag
432 Don\'t multiply the pbl/txpbl/rxpbl values by 8. For core
433 rev < 3.50, don\'t multiply the values by 4.
440 - allwinner,sun7i-a20-gmac
441 - allwinner,sun8i-a83t-emac
442 - allwinner,sun8i-h3-emac
443 - allwinner,sun8i-r40-gmac
444 - allwinner,sun8i-v3s-emac
445 - allwinner,sun50i-a64-emac
446 - loongson,ls2k-dwmac
447 - loongson,ls7a-dwmac
465 $ref: /schemas/types.yaml#/definitions/flag
467 Enables the TSO feature otherwise it will be managed by
468 MAC HW capability register.
470 additionalProperties: true
474 stmmac_axi_setup: stmmac-axi-config {
475 snps,wr_osr_lmt = <0xf>;
476 snps,rd_osr_lmt = <0xf>;
477 snps,blen = <256 128 64 32 0 0 0>;
480 mtl_rx_setup: rx-queues-config {
481 snps,rx-queues-to-use = <1>;
485 snps,map-to-dma-channel = <0x0>;
486 snps,priority = <0x0>;
490 mtl_tx_setup: tx-queues-config {
491 snps,tx-queues-to-use = <2>;
494 snps,weight = <0x10>;
496 snps,priority = <0x0>;
501 snps,send_slope = <0x1000>;
502 snps,idle_slope = <0x1000>;
503 snps,high_credit = <0x3E800>;
504 snps,low_credit = <0xFFC18000>;
505 snps,priority = <0x1>;
509 gmac0: ethernet@e0800000 {
510 compatible = "snps,dwxgmac-2.10", "snps,dwxgmac";
511 reg = <0xe0800000 0x8000>;
512 interrupt-parent = <&vic1>;
513 interrupts = <24 23 22>;
514 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
515 mac-address = [000000000000]; /* Filled in by U-Boot */
516 max-frame-size = <3800>;
518 snps,multicast-filter-bins = <256>;
519 snps,perfect-filter-entries = <128>;
520 rx-fifo-depth = <16384>;
521 tx-fifo-depth = <16384>;
523 clock-names = "stmmaceth";
524 snps,axi-config = <&stmmac_axi_setup>;
525 snps,mtl-rx-config = <&mtl_rx_setup>;
526 snps,mtl-tx-config = <&mtl_tx_setup>;
528 #address-cells = <1>;
530 compatible = "snps,dwmac-mdio";
531 phy1: ethernet-phy@0 {
537 # FIXME: We should set it, but it would report all the generic
538 # properties as additional properties.
539 # additionalProperties: false