1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare MAC
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
14 # Select every compatible, including the deprecated ones. This way, we
15 # will be able to report a warning when we have that compatible, since
16 # we will validate the node thanks to the select, but won't report it
17 # as a valid value in the compatible property description
44 # We need to include all the compatibles from schemas that will
45 # include that schemas, otherwise compatible won't validate for
50 - allwinner,sun7i-a20-gmac
51 - allwinner,sun8i-a83t-emac
52 - allwinner,sun8i-h3-emac
53 - allwinner,sun8i-r40-gmac
54 - allwinner,sun8i-v3s-emac
55 - allwinner,sun50i-a64-emac
56 - amlogic,meson6-dwmac
57 - amlogic,meson8b-dwmac
58 - amlogic,meson8m2-dwmac
59 - amlogic,meson-gxbb-dwmac
60 - amlogic,meson-axg-dwmac
68 - renesas,r9a06g032-gmac
71 - rockchip,rk3128-gmac
72 - rockchip,rk3228-gmac
73 - rockchip,rk3288-gmac
74 - rockchip,rk3328-gmac
75 - rockchip,rk3366-gmac
76 - rockchip,rk3368-gmac
77 - rockchip,rk3588-gmac
78 - rockchip,rk3399-gmac
79 - rockchip,rv1108-gmac
100 - description: Combined signal for various interrupt events
101 - description: The interrupt to manage the remote wake-up packet detection
102 - description: The interrupt that occurs when Rx exits the LPI state
108 - const: eth_wake_irq
114 additionalItems: true
116 - description: GMAC main clock
117 - description: Peripheral registers interface clock
119 PTP reference clock. This clock is used for programming the
120 Timestamp Addend Register. If not passed then the system
121 clock will be used and this is fine on some platforms.
126 additionalItems: true
145 $ref: ethernet-controller.yaml#/properties/phy-connection-type
147 The property is identical to 'phy-mode', and assumes that there is mode
148 converter in-between the MAC & PHY (e.g. GMII-to-RGMII). This converter
149 can be passive (no SW requirement), and requires that the MAC operate
150 in a different mode than the PHY in order to function.
153 $ref: /schemas/types.yaml#/definitions/phandle
155 AXI BUS Mode parameters. Phandle to a node that can contain the
157 * snps,lpi_en, enable Low Power Interface
158 * snps,xit_frm, unlock on WoL
159 * snps,wr_osr_lmt, max write outstanding req. limit
160 * snps,rd_osr_lmt, max read outstanding req. limit
161 * snps,kbbe, do not cross 1KiB boundary.
162 * snps,blen, this is a vector of supported burst length.
163 * snps,fb, fixed-burst
164 * snps,mb, mixed-burst
165 * snps,rb, rebuild INCRx Burst
168 $ref: /schemas/types.yaml#/definitions/phandle
170 Multiple RX Queues parameters. Phandle to a node that can
171 contain the following properties
172 * snps,rx-queues-to-use, number of RX queues to be used in the
174 * Choose one of these RX scheduling algorithms
175 * snps,rx-sched-sp, Strict priority
176 * snps,rx-sched-wsp, Weighted Strict priority
178 * Choose one of these modes
179 * snps,dcb-algorithm, Queue to be enabled as DCB
180 * snps,avb-algorithm, Queue to be enabled as AVB
181 * snps,map-to-dma-channel, Channel to map
182 * Specifiy specific packet routing
183 * snps,route-avcp, AV Untagged Control packets
184 * snps,route-ptp, PTP Packets
185 * snps,route-dcbcp, DCB Control Packets
186 * snps,route-up, Untagged Packets
187 * snps,route-multi-broad, Multicast & Broadcast Packets
188 * snps,priority, bitmask of the tagged frames priorities assigned to
192 $ref: /schemas/types.yaml#/definitions/phandle
194 Multiple TX Queues parameters. Phandle to a node that can
195 contain the following properties
196 * snps,tx-queues-to-use, number of TX queues to be used in the
198 * Choose one of these TX scheduling algorithms
199 * snps,tx-sched-wrr, Weighted Round Robin
200 * snps,tx-sched-wfq, Weighted Fair Queuing
201 * snps,tx-sched-dwrr, Deficit Weighted Round Robin
202 * snps,tx-sched-sp, Strict priority
204 * snps,weight, TX queue weight (if using a DCB weight
206 * Choose one of these modes
207 * snps,dcb-algorithm, TX queue will be working in DCB
208 * snps,avb-algorithm, TX queue will be working in AVB
209 [Attention] Queue 0 is reserved for legacy traffic
210 and so no AVB is available in this queue.
211 * Configure Credit Base Shaper (if AVB Mode selected)
212 * snps,send_slope, enable Low Power Interface
213 * snps,idle_slope, unlock on WoL
214 * snps,high_credit, max write outstanding req. limit
215 * snps,low_credit, max read outstanding req. limit
216 * snps,priority, bitmask of the priorities assigned to the queue.
217 When a PFC frame is received with priorities matching the bitmask,
218 the queue is blocked from transmitting for the pause time specified
227 snps,reset-active-low:
229 $ref: /schemas/types.yaml#/definitions/flag
231 Indicates that the PHY Reset is active low
233 snps,reset-delays-us:
236 Triplet of delays. The 1st cell is reset pre-delay in micro
237 seconds. The 2nd cell is reset pulse in micro seconds. The 3rd
238 cell is reset post-delay in micro seconds.
243 $ref: /schemas/types.yaml#/definitions/flag
245 Use Address-Aligned Beats
248 $ref: /schemas/types.yaml#/definitions/flag
250 Program the DMA to use the fixed burst mode
253 $ref: /schemas/types.yaml#/definitions/flag
255 Program the DMA to use the mixed burst mode
257 snps,force_thresh_dma_mode:
258 $ref: /schemas/types.yaml#/definitions/flag
260 Force DMA to use the threshold mode for both tx and rx
262 snps,force_sf_dma_mode:
263 $ref: /schemas/types.yaml#/definitions/flag
265 Force DMA to use the Store and Forward mode for both tx and
266 rx. This flag is ignored if force_thresh_dma_mode is set.
268 snps,en-tx-lpi-clockgating:
269 $ref: /schemas/types.yaml#/definitions/flag
271 Enable gating of the MAC TX clock during TX low-power mode
273 snps,multicast-filter-bins:
274 $ref: /schemas/types.yaml#/definitions/uint32
276 Number of multicast filter hash bins supported by this device
279 snps,perfect-filter-entries:
280 $ref: /schemas/types.yaml#/definitions/uint32
282 Number of perfect filter entries supported by this device
286 $ref: /schemas/types.yaml#/definitions/uint32
288 Port selection speed that can be passed to the core when PCS
289 is supported. For example, this is used in case of SGMII and
293 $ref: /schemas/types.yaml#/definitions/uint32
295 Frequency division factor for MDC clock.
299 unevaluatedProperties: false
301 Creates and registers an MDIO bus.
305 const: snps,dwmac-mdio
312 unevaluatedProperties: false
314 AXI BUS Mode parameters.
318 $ref: /schemas/types.yaml#/definitions/flag
320 enable Low Power Interface
323 $ref: /schemas/types.yaml#/definitions/flag
328 $ref: /schemas/types.yaml#/definitions/uint32
330 max write outstanding req. limit
333 $ref: /schemas/types.yaml#/definitions/uint32
335 max read outstanding req. limit
338 $ref: /schemas/types.yaml#/definitions/uint32
340 do not cross 1KiB boundary.
343 $ref: /schemas/types.yaml#/definitions/uint32-array
345 this is a vector of supported burst length.
350 $ref: /schemas/types.yaml#/definitions/flag
355 $ref: /schemas/types.yaml#/definitions/flag
360 $ref: /schemas/types.yaml#/definitions/flag
372 snps,reset-active-low: ["snps,reset-gpio"]
373 snps,reset-delay-us: ["snps,reset-gpio"]
376 - $ref: "ethernet-controller.yaml#"
382 - allwinner,sun7i-a20-gmac
383 - allwinner,sun8i-a83t-emac
384 - allwinner,sun8i-h3-emac
385 - allwinner,sun8i-r40-gmac
386 - allwinner,sun8i-v3s-emac
387 - allwinner,sun50i-a64-emac
404 Programmable Burst Length (tx and rx)
405 $ref: /schemas/types.yaml#/definitions/uint32
406 enum: [1, 2, 4, 8, 16, 32]
410 Tx Programmable Burst Length. If set, DMA tx will use this
411 value rather than snps,pbl.
412 $ref: /schemas/types.yaml#/definitions/uint32
413 enum: [1, 2, 4, 8, 16, 32]
417 Rx Programmable Burst Length. If set, DMA rx will use this
418 value rather than snps,pbl.
419 $ref: /schemas/types.yaml#/definitions/uint32
420 enum: [1, 2, 4, 8, 16, 32]
423 $ref: /schemas/types.yaml#/definitions/flag
425 Don\'t multiply the pbl/txpbl/rxpbl values by 8. For core
426 rev < 3.50, don\'t multiply the values by 4.
433 - allwinner,sun7i-a20-gmac
434 - allwinner,sun8i-a83t-emac
435 - allwinner,sun8i-h3-emac
436 - allwinner,sun8i-r40-gmac
437 - allwinner,sun8i-v3s-emac
438 - allwinner,sun50i-a64-emac
439 - loongson,ls2k-dwmac
440 - loongson,ls7a-dwmac
457 $ref: /schemas/types.yaml#/definitions/flag
459 Enables the TSO feature otherwise it will be managed by
460 MAC HW capability register.
462 additionalProperties: true
466 stmmac_axi_setup: stmmac-axi-config {
467 snps,wr_osr_lmt = <0xf>;
468 snps,rd_osr_lmt = <0xf>;
469 snps,blen = <256 128 64 32 0 0 0>;
472 mtl_rx_setup: rx-queues-config {
473 snps,rx-queues-to-use = <1>;
477 snps,map-to-dma-channel = <0x0>;
478 snps,priority = <0x0>;
482 mtl_tx_setup: tx-queues-config {
483 snps,tx-queues-to-use = <2>;
486 snps,weight = <0x10>;
488 snps,priority = <0x0>;
493 snps,send_slope = <0x1000>;
494 snps,idle_slope = <0x1000>;
495 snps,high_credit = <0x3E800>;
496 snps,low_credit = <0xFFC18000>;
497 snps,priority = <0x1>;
501 gmac0: ethernet@e0800000 {
502 compatible = "snps,dwxgmac-2.10", "snps,dwxgmac";
503 reg = <0xe0800000 0x8000>;
504 interrupt-parent = <&vic1>;
505 interrupts = <24 23 22>;
506 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
507 mac-address = [000000000000]; /* Filled in by U-Boot */
508 max-frame-size = <3800>;
510 snps,multicast-filter-bins = <256>;
511 snps,perfect-filter-entries = <128>;
512 rx-fifo-depth = <16384>;
513 tx-fifo-depth = <16384>;
515 clock-names = "stmmaceth";
516 snps,axi-config = <&stmmac_axi_setup>;
517 snps,mtl-rx-config = <&mtl_rx_setup>;
518 snps,mtl-tx-config = <&mtl_tx_setup>;
520 #address-cells = <1>;
522 compatible = "snps,dwmac-mdio";
523 phy1: ethernet-phy@0 {
529 # FIXME: We should set it, but it would report all the generic
530 # properties as additional properties.
531 # additionalProperties: false