1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/rockchip-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip 10/100/1000 Ethernet driver(GMAC)
10 - David Wu <david.wu@rock-chips.com>
12 # We need a select here so we don't match all nodes with 'snps,dwmac'
19 - rockchip,rk3128-gmac
20 - rockchip,rk3228-gmac
21 - rockchip,rk3288-gmac
22 - rockchip,rk3308-gmac
23 - rockchip,rk3328-gmac
24 - rockchip,rk3366-gmac
25 - rockchip,rk3368-gmac
26 - rockchip,rk3399-gmac
27 - rockchip,rk3568-gmac
28 - rockchip,rk3588-gmac
29 - rockchip,rv1108-gmac
30 - rockchip,rv1126-gmac
35 - $ref: snps,dwmac.yaml#
43 - rockchip,rk3128-gmac
44 - rockchip,rk3228-gmac
45 - rockchip,rk3288-gmac
46 - rockchip,rk3308-gmac
47 - rockchip,rk3328-gmac
48 - rockchip,rk3366-gmac
49 - rockchip,rk3368-gmac
50 - rockchip,rk3399-gmac
51 - rockchip,rv1108-gmac
54 - rockchip,rk3568-gmac
55 - rockchip,rk3588-gmac
56 - rockchip,rv1126-gmac
57 - const: snps,dwmac-4.20a
77 For RGMII, it must be "input", means main clock(125MHz)
78 is not sourced from SoC's PLL, but input from PHY.
79 For RMII, "input" means PHY provides the reference clock(50MHz),
80 "output" means GMAC provides the reference clock.
81 $ref: /schemas/types.yaml#/definitions/string
85 description: The phandle of the syscon node for the general register file.
86 $ref: /schemas/types.yaml#/definitions/phandle
90 The phandle of the syscon node for the peripheral general register file.
91 $ref: /schemas/types.yaml#/definitions/phandle
94 description: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
95 $ref: /schemas/types.yaml#/definitions/uint32
98 description: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
99 $ref: /schemas/types.yaml#/definitions/uint32
102 description: PHY regulator
109 unevaluatedProperties: false
113 #include <dt-bindings/interrupt-controller/arm-gic.h>
114 #include <dt-bindings/clock/rk3288-cru.h>
116 gmac: ethernet@ff290000 {
117 compatible = "rockchip,rk3288-gmac";
118 reg = <0xff290000 0x10000>;
119 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
120 interrupt-names = "macirq";
121 clocks = <&cru SCLK_MAC>,
122 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
123 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
124 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
125 clock-names = "stmmaceth",
126 "mac_clk_rx", "mac_clk_tx",
127 "clk_mac_ref", "clk_mac_refout",
128 "aclk_mac", "pclk_mac";
129 assigned-clocks = <&cru SCLK_MAC>;
130 assigned-clock-parents = <&ext_gmac>;
132 rockchip,grf = <&grf>;
134 clock_in_out = "input";