1 MediaTek Frame Engine Ethernet controller
2 =========================================
4 The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
5 have dual GMAC each represented by a child node..
7 * Ethernet controller node
10 - compatible: Should be
11 "mediatek,mt2701-eth": for MT2701 SoC
12 "mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
13 "mediatek,mt7622-eth": for MT7622 SoC
14 "mediatek,mt7629-eth": for MT7629 SoC
15 - reg: Address and length of the register set for the device
16 - interrupts: Should contain the three frame engines interrupts in numeric
17 order. These are fe_int0, fe_int1 and fe_int2.
18 - clocks: the clock used by the core
19 - clock-names: the names of the clock listed in the clocks property. These are
20 "ethif", "esw", "gp2", "gp1" : For MT2701 and MT7623 SoC
21 "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m",
22 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC
23 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "sgmii_tx250m",
24 "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii2_tx250m",
25 "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", "sgmii_ck",
26 "eth2pll" : For MT7629 SoC.
27 - power-domains: phandle to the power domain that the ethernet is part of
28 - resets: Should contain phandles to the ethsys reset signals
29 - reset-names: Should contain the names of reset signal listed in the resets
31 These are "fe", "gmac" and "ppe"
32 - mediatek,ethsys: phandle to the syscon node that handles the port setup
33 - mediatek,infracfg: phandle to the syscon node that handles the path from
34 GMAC to PHY variants, which is required for MT7629 SoC.
35 - mediatek,sgmiisys: a list of phandles to the syscon node that handles the
36 SGMII setup which is required for those SoCs equipped with SGMII such
37 as MT7622 and MT7629 SoC. And MT7622 have only one set of SGMII shared
38 by GMAC1 and GMAC2; MT7629 have two independent sets of SGMII directed
39 to GMAC1 and GMAC2, respectively.
40 - mediatek,pctl: phandle to the syscon node that handles the ports slew rate
41 and driver current: only for MT2701 and MT7623 SoC
46 - compatible: Should be "mediatek,eth-mac"
47 - reg: The number of the MAC
48 - phy-handle: see ethernet.txt file in the same directory and
49 the phy-mode "trgmii" required being provided when reg
50 is equal to 0 and the MAC uses fixed-link to connect
51 with internal switch such as MT7530.
55 eth: ethernet@1b100000 {
56 compatible = "mediatek,mt7623-eth";
57 reg = <0 0x1b100000 0 0x20000>;
58 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
59 <ðsys CLK_ETHSYS_ESW>,
60 <ðsys CLK_ETHSYS_GP2>,
61 <ðsys CLK_ETHSYS_GP1>;
62 clock-names = "ethif", "esw", "gp2", "gp1";
63 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
64 GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
65 GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
66 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
67 resets = <ðsys MT2701_ETHSYS_ETH_RST>;
69 mediatek,ethsys = <ðsys>;
70 mediatek,pctl = <&syscfg_pctl_a>;
75 compatible = "mediatek,eth-mac";
81 compatible = "mediatek,eth-mac";
87 phy0: ethernet-phy@0 {
92 phy1: ethernet-phy@1 {