Documentation/devicetree/bindings/net/imx-dwmac.txt

   1 IMX8 glue layer controller, NXP imx8 families support Synopsys MAC 5.10a IP.
   2
   3 This file documents platform glue layer for IMX.
   4 Please see stmmac.txt for the other unchanged properties.
   5
   6 The device node has following properties.
   7
   8 Required properties:
   9 - compatible:  Should be "nxp,imx8mp-dwmac-eqos" to select glue layer
  10                and "snps,dwmac-5.10a" to select IP version.
  11 - clocks: Must contain a phandle for each entry in clock-names.
  12 - clock-names: Should be "stmmaceth" for the host clock.
  13                Should be "pclk" for the MAC apb clock.
  14                Should be "ptp_ref" for the MAC timer clock.
  15                Should be "tx" for the MAC RGMII TX clock:
  16                Should be "mem" for EQOS MEM clock.
  17                 - "mem" clock is required for imx8dxl platform.
  18                 - "mem" clock is not required for imx8mp platform.
  19 - interrupt-names: Should contain a list of interrupt names corresponding to
  20                    the interrupts in the interrupts property, if available.
  21                    Should be "macirq" for the main MAC IRQ
  22                    Should be "eth_wake_irq" for the IT which wake up system
  23 - intf_mode: Should be phandle/offset pair. The phandle to the syscon node which
  24              encompases the GPR register, and the offset of the GPR register.
  25                 - required for imx8mp platform.
  26                 - is optional for imx8dxl platform.
  27
  28 Optional properties:
  29 - intf_mode: is optional for imx8dxl platform.
  30 - snps,rmii_refclk_ext: to select RMII reference clock from external.
  31
  32 Example:
  33         eqos: ethernet@30bf0000 {
  34                 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
  35                 reg = <0x30bf0000 0x10000>;
  36                 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
  37                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
  38                 interrupt-names = "eth_wake_irq", "macirq";
  39                 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
  40                          <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
  41                          <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
  42                          <&clk IMX8MP_CLK_ENET_QOS>;
  43                 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
  44                 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
  45                                   <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
  46                                   <&clk IMX8MP_CLK_ENET_QOS>;
  47                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
  48                                          <&clk IMX8MP_SYS_PLL2_100M>,
  49                                          <&clk IMX8MP_SYS_PLL2_125M>;
  50                 assigned-clock-rates = <0>, <100000000>, <125000000>;
  51                 nvmem-cells = <&eth_mac0>;
  52                 nvmem-cell-names = "mac-address";
  53                 nvmem_macaddr_swap;
  54                 intf_mode = <&gpr 0x4>;
  55                 status = "disabled";
  56         };