Documentation/devicetree/bindings/net/cdns,macb.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/net/cdns,macb.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Cadence MACB/GEM Ethernet controller
   8
   9 maintainers:
  10   - Nicolas Ferre <nicolas.ferre@microchip.com>
  11   - Claudiu Beznea <claudiu.beznea@microchip.com>
  12
  13 properties:
  14   compatible:
  15     oneOf:
  16       - items:
  17           - enum:
  18               - cdns,at91rm9200-emac  # Atmel at91rm9200 SoC
  19           - const: cdns,emac          # Generic
  20
  21       - items:
  22           - enum:
  23               - cdns,zynq-gem         # Xilinx Zynq-7xxx SoC
  24               - cdns,zynqmp-gem       # Xilinx Zynq Ultrascale+ MPSoC
  25           - const: cdns,gem           # Generic
  26         deprecated: true
  27
  28       - items:
  29           - enum:
  30               - xlnx,versal-gem       # Xilinx Versal
  31               - xlnx,zynq-gem         # Xilinx Zynq-7xxx SoC
  32               - xlnx,zynqmp-gem       # Xilinx Zynq Ultrascale+ MPSoC
  33           - const: cdns,gem           # Generic
  34
  35       - items:
  36           - enum:
  37               - cdns,at91sam9260-macb # Atmel at91sam9 SoCs
  38               - cdns,sam9x60-macb     # Microchip sam9x60 SoC
  39               - microchip,mpfs-macb   # Microchip PolarFire SoC
  40           - const: cdns,macb          # Generic
  41
  42       - items:
  43           - enum:
  44               - atmel,sama5d3-macb    # 10/100Mbit IP on Atmel sama5d3 SoCs
  45           - enum:
  46               - cdns,at91sam9260-macb # Atmel at91sam9 SoCs.
  47           - const: cdns,macb          # Generic
  48
  49       - enum:
  50           - atmel,sama5d29-gem        # GEM XL IP (10/100) on Atmel sama5d29 SoCs
  51           - atmel,sama5d2-gem         # GEM IP (10/100) on Atmel sama5d2 SoCs
  52           - atmel,sama5d3-gem         # Gigabit IP on Atmel sama5d3 SoCs
  53           - atmel,sama5d4-gem         # GEM IP (10/100) on Atmel sama5d4 SoCs
  54           - cdns,np4-macb             # NP4 SoC devices
  55           - microchip,sama7g5-emac    # Microchip SAMA7G5 ethernet interface
  56           - microchip,sama7g5-gem     # Microchip SAMA7G5 gigabit ethernet interface
  57           - sifive,fu540-c000-gem     # SiFive FU540-C000 SoC
  58           - cdns,emac                 # Generic
  59           - cdns,gem                  # Generic
  60           - cdns,macb                 # Generic
  61
  62   reg:
  63     minItems: 1
  64     items:
  65       - description: Basic register set
  66       - description: GEMGXL Management block registers on SiFive FU540-C000 SoC
  67
  68   interrupts:
  69     minItems: 1
  70     maxItems: 8
  71     description: One interrupt per available hardware queue
  72
  73   clocks:
  74     minItems: 1
  75     maxItems: 5
  76
  77   clock-names:
  78     minItems: 1
  79     items:
  80       - enum: [ ether_clk, hclk, pclk ]
  81       - enum: [ hclk, pclk ]
  82       - const: tx_clk
  83       - enum: [ rx_clk, tsu_clk ]
  84       - const: tsu_clk
  85
  86   local-mac-address: true
  87
  88   phy-mode: true
  89
  90   phy-handle: true
  91
  92   phys:
  93     maxItems: 1
  94
  95   resets:
  96     maxItems: 1
  97     description:
  98       Recommended with ZynqMP, specify reset control for this
  99       controller instance with zynqmp-reset driver.
 100
 101   reset-names:
 102     maxItems: 1
 103
 104   fixed-link: true
 105
 106   iommus:
 107     maxItems: 1
 108
 109   power-domains:
 110     maxItems: 1
 111
 112   cdns,rx-watermark:
 113     $ref: /schemas/types.yaml#/definitions/uint32
 114     description:
 115       When the receive partial store and forward mode is activated,
 116       the receiver will only begin to forward the packet to the external
 117       AHB or AXI slave when enough packet data is stored in the SRAM packet buffer.
 118       rx-watermark corresponds to the number of SRAM buffer locations,
 119       that need to be filled, before the forwarding process is activated.
 120       Width of the SRAM is platform dependent, and can be 4, 8 or 16 bytes.
 121
 122   '#address-cells':
 123     const: 1
 124
 125   '#size-cells':
 126     const: 0
 127
 128   mdio:
 129     type: object
 130     description:
 131       Node containing PHY children. If this node is not present, then PHYs will
 132       be direct children.
 133
 134   cdns,aw2w-max-pipe:
 135     $ref: /schemas/types.yaml#/definitions/uint32
 136     description:
 137       Maximum number of outstanding AXI write requests
 138
 139   cdns,ar2r-max-pipe:
 140     $ref: /schemas/types.yaml#/definitions/uint32
 141     description:
 142       Maximum number of outstanding AXI read requests
 143
 144   cdns,use-aw2b-fill:
 145     type: boolean
 146     description:
 147       If set, the maximum number of outstanding write transactions operates
 148       between the AW to B AXI channel, instead of the AW to W AXI channel.
 149
 150 patternProperties:
 151   "^ethernet-phy@[0-9a-f]$":
 152     type: object
 153     $ref: ethernet-phy.yaml#
 154
 155     properties:
 156       reset-gpios: true
 157
 158       magic-packet:
 159         type: boolean
 160         description:
 161           Indicates that the hardware supports waking up via magic packet.
 162
 163     unevaluatedProperties: false
 164
 165 required:
 166   - compatible
 167   - reg
 168   - interrupts
 169   - clocks
 170   - clock-names
 171   - phy-mode
 172
 173 allOf:
 174   - $ref: ethernet-controller.yaml#
 175
 176   - if:
 177       not:
 178         properties:
 179           compatible:
 180             contains:
 181               const: sifive,fu540-c000-gem
 182     then:
 183       properties:
 184         reg:
 185           maxItems: 1
 186
 187 unevaluatedProperties: false
 188
 189 examples:
 190   - |
 191     macb0: ethernet@fffc4000 {
 192             compatible = "cdns,macb";
 193             reg = <0xfffc4000 0x4000>;
 194             interrupts = <21>;
 195             cdns,rx-watermark = <0x44>;
 196             phy-mode = "rmii";
 197             local-mac-address = [3a 0e 03 04 05 06];
 198             clock-names = "pclk", "hclk", "tx_clk";
 199             clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
 200             #address-cells = <1>;
 201             #size-cells = <0>;
 202
 203             ethernet-phy@1 {
 204                     reg = <0x1>;
 205                     reset-gpios = <&pioE 6 1>;
 206             };
 207     };
 208
 209   - |
 210     #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
 211     #include <dt-bindings/power/xlnx-zynqmp-power.h>
 212     #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
 213     #include <dt-bindings/phy/phy.h>
 214
 215     bus {
 216             #address-cells = <2>;
 217             #size-cells = <2>;
 218             gem1: ethernet@ff0c0000 {
 219                     compatible = "xlnx,zynqmp-gem", "cdns,gem";
 220                     interrupt-parent = <&gic>;
 221                     interrupts = <0 59 4>, <0 59 4>;
 222                     reg = <0x0 0xff0c0000 0x0 0x1000>;
 223                     clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
 224                              <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
 225                              <&zynqmp_clk GEM_TSU>;
 226                     clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 227                     #address-cells = <1>;
 228                     #size-cells = <0>;
 229                     iommus = <&smmu 0x875>;
 230                     power-domains = <&zynqmp_firmware PD_ETH_1>;
 231                     resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
 232                     reset-names = "gem1_rst";
 233                     phy-mode = "sgmii";
 234                     phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>;
 235                     fixed-link {
 236                             speed = <1000>;
 237                             full-duplex;
 238                             pause;
 239                     };
 240             };
 241     };