Documentation/devicetree/bindings/mmc/sdhci-am654.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
   6 $schema : "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: TI AM654 MMC Controller
   9
  10 maintainers:
  11   - Ulf Hansson <ulf.hansson@linaro.org>
  12
  13 allOf:
  14   - $ref: mmc-controller.yaml#
  15
  16 properties:
  17   compatible:
  18     enum:
  19       - ti,am654-sdhci-5.1
  20       - ti,j721e-sdhci-8bit
  21       - ti,j721e-sdhci-4bit
  22       - ti,j7200-sdhci-8bit
  23       - ti,j721e-sdhci-4bit
  24
  25   reg:
  26     maxItems: 2
  27
  28   interrupts:
  29     maxItems: 1
  30
  31   power-domains:
  32     maxItems: 1
  33
  34   clocks:
  35     minItems: 1
  36     maxItems: 2
  37     description: Handles to input clocks
  38
  39   clock-names:
  40     minItems: 1
  41     maxItems: 2
  42     items:
  43       - const: clk_ahb
  44       - const: clk_xin
  45
  46   # PHY output tap delays:
  47   # Used to delay the data valid window and align it to the sampling clock.
  48   # Binding needs to be provided for each supported speed mode otherwise the
  49   # corresponding mode will be disabled.
  50
  51   ti,otap-del-sel-legacy:
  52     description: Output tap delay for SD/MMC legacy timing
  53     $ref: "/schemas/types.yaml#/definitions/uint32"
  54     minimum: 0
  55     maximum: 0xf
  56
  57   ti,otap-del-sel-mmc-hs:
  58     description: Output tap delay for MMC high speed timing
  59     $ref: "/schemas/types.yaml#/definitions/uint32"
  60     minimum: 0
  61     maximum: 0xf
  62
  63   ti,otap-del-sel-sd-hs:
  64     description: Output tap delay for SD high speed timing
  65     $ref: "/schemas/types.yaml#/definitions/uint32"
  66     minimum: 0
  67     maximum: 0xf
  68
  69   ti,otap-del-sel-sdr12:
  70     description: Output tap delay for SD UHS SDR12 timing
  71     $ref: "/schemas/types.yaml#/definitions/uint32"
  72     minimum: 0
  73     maximum: 0xf
  74
  75   ti,otap-del-sel-sdr25:
  76     description: Output tap delay for SD UHS SDR25 timing
  77     $ref: "/schemas/types.yaml#/definitions/uint32"
  78     minimum: 0
  79     maximum: 0xf
  80
  81   ti,otap-del-sel-sdr50:
  82     description: Output tap delay for SD UHS SDR50 timing
  83     $ref: "/schemas/types.yaml#/definitions/uint32"
  84     minimum: 0
  85     maximum: 0xf
  86
  87   ti,otap-del-sel-sdr104:
  88     description: Output tap delay for SD UHS SDR104 timing
  89     $ref: "/schemas/types.yaml#/definitions/uint32"
  90     minimum: 0
  91     maximum: 0xf
  92
  93   ti,otap-del-sel-ddr50:
  94     description: Output tap delay for SD UHS DDR50 timing
  95     $ref: "/schemas/types.yaml#/definitions/uint32"
  96     minimum: 0
  97     maximum: 0xf
  98
  99   ti,otap-del-sel-ddr52:
 100     description: Output tap delay for eMMC DDR52 timing
 101     $ref: "/schemas/types.yaml#/definitions/uint32"
 102     minimum: 0
 103     maximum: 0xf
 104
 105   ti,otap-del-sel-hs200:
 106     description: Output tap delay for eMMC HS200 timing
 107     $ref: "/schemas/types.yaml#/definitions/uint32"
 108     minimum: 0
 109     maximum: 0xf
 110
 111   ti,otap-del-sel-hs400:
 112     description: Output tap delay for eMMC HS400 timing
 113     $ref: "/schemas/types.yaml#/definitions/uint32"
 114     minimum: 0
 115     maximum: 0xf
 116
 117   # PHY input tap delays:
 118   # Used to delay the data valid window and align it to the sampling clock for
 119   # modes that don't support tuning
 120
 121   ti,itap-del-sel-legacy:
 122     description: Input tap delay for SD/MMC legacy timing
 123     $ref: "/schemas/types.yaml#/definitions/uint32"
 124     minimum: 0
 125     maximum: 0x1f
 126
 127   ti,itap-del-sel-mmc-hs:
 128     description: Input tap delay for MMC high speed timing
 129     $ref: "/schemas/types.yaml#/definitions/uint32"
 130     minimum: 0
 131     maximum: 0x1f
 132
 133   ti,itap-del-sel-sd-hs:
 134     description: Input tap delay for SD high speed timing
 135     $ref: "/schemas/types.yaml#/definitions/uint32"
 136     minimum: 0
 137     maximum: 0x1f
 138
 139   ti,itap-del-sel-sdr12:
 140     description: Input tap delay for SD UHS SDR12 timing
 141     $ref: "/schemas/types.yaml#/definitions/uint32"
 142     minimum: 0
 143     maximum: 0x1f
 144
 145   ti,itap-del-sel-sdr25:
 146     description: Input tap delay for SD UHS SDR25 timing
 147     $ref: "/schemas/types.yaml#/definitions/uint32"
 148     minimum: 0
 149     maximum: 0x1f
 150
 151   ti,itap-del-sel-ddr52:
 152     description: Input tap delay for MMC DDR52 timing
 153     $ref: "/schemas/types.yaml#/definitions/uint32"
 154     minimum: 0
 155     maximum: 0x1f
 156
 157   ti,trm-icp:
 158     description: DLL trim select
 159     $ref: "/schemas/types.yaml#/definitions/uint32"
 160     minimum: 0
 161     maximum: 0xf
 162
 163   ti,driver-strength-ohm:
 164     description: DLL drive strength in ohms
 165     $ref: "/schemas/types.yaml#/definitions/uint32"
 166     oneOf:
 167       - enum:
 168         - 33
 169         - 40
 170         - 50
 171         - 66
 172         - 100
 173
 174   ti,strobe-sel:
 175     description: strobe select delay for HS400 speed mode.
 176     $ref: "/schemas/types.yaml#/definitions/uint32"
 177
 178   ti,clkbuf-sel:
 179     description: Clock Delay Buffer Select
 180     $ref: "/schemas/types.yaml#/definitions/uint32"
 181
 182 required:
 183   - compatible
 184   - reg
 185   - interrupts
 186   - clocks
 187   - clock-names
 188   - ti,otap-del-sel-legacy
 189
 190 examples:
 191   - |
 192     #include <dt-bindings/interrupt-controller/irq.h>
 193     #include <dt-bindings/interrupt-controller/arm-gic.h>
 194
 195     bus {
 196         #address-cells = <2>;
 197         #size-cells = <2>;
 198
 199         mmc0: mmc@4f80000 {
 200             compatible = "ti,am654-sdhci-5.1";
 201             reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
 202             power-domains = <&k3_pds 47>;
 203             clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
 204             clock-names = "clk_ahb", "clk_xin";
 205             interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 206             sdhci-caps-mask = <0x80000007 0x0>;
 207             mmc-ddr-1_8v;
 208             ti,otap-del-sel-legacy = <0x0>;
 209             ti,otap-del-sel-mmc-hs = <0x0>;
 210             ti,otap-del-sel-ddr52 = <0x5>;
 211             ti,otap-del-sel-hs200 = <0x5>;
 212             ti,otap-del-sel-hs400 = <0x0>;
 213             ti,itap-del-sel-legacy = <0x10>;
 214             ti,itap-del-sel-mmc-hs = <0xa>;
 215             ti,itap-del-sel-ddr52 = <0x3>;
 216             ti,trm-icp = <0x8>;
 217         };
 218     };