Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Synopsys IntelliDDR Multi Protocol memory controller
   8
   9 maintainers:
  10   - Krzysztof Kozlowski <krzk@kernel.org>
  11   - Manish Narani <manish.narani@xilinx.com>
  12   - Michal Simek <michal.simek@xilinx.com>
  13
  14 description: |
  15   The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
  16   32-bit bus width configurations.
  17
  18   The Zynq DDR ECC controller has an optional ECC support in half-bus width
  19   (16-bit) configuration.
  20
  21   These both ECC controllers correct single bit ECC errors and detect double bit
  22   ECC errors.
  23
  24 properties:
  25   compatible:
  26     enum:
  27       - snps,ddrc-3.80a
  28       - xlnx,zynq-ddrc-a05
  29       - xlnx,zynqmp-ddrc-2.40a
  30
  31   interrupts:
  32     maxItems: 1
  33
  34   reg:
  35     maxItems: 1
  36
  37 required:
  38   - compatible
  39   - reg
  40
  41 allOf:
  42   - if:
  43       properties:
  44         compatible:
  45           contains:
  46             enum:
  47               - snps,ddrc-3.80a
  48               - xlnx,zynqmp-ddrc-2.40a
  49     then:
  50       required:
  51         - interrupts
  52     else:
  53       properties:
  54         interrupts: false
  55
  56 additionalProperties: false
  57
  58 examples:
  59   - |
  60     memory-controller@f8006000 {
  61         compatible = "xlnx,zynq-ddrc-a05";
  62         reg = <0xf8006000 0x1000>;
  63     };
  64
  65   - |
  66     axi {
  67         #address-cells = <2>;
  68         #size-cells = <2>;
  69
  70         memory-controller@fd070000 {
  71             compatible = "xlnx,zynqmp-ddrc-2.40a";
  72             reg = <0x0 0xfd070000 0x0 0x30000>;
  73             interrupt-parent = <&gic>;
  74             interrupts = <0 112 4>;
  75         };
  76     };