Documentation/devicetree/bindings/media/samsung,fimc.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/media/samsung,fimc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Samsung S5P/Exynos SoC Camera Subsystem (FIMC)
   8
   9 maintainers:
  10   - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  11   - Sylwester Nawrocki <s.nawrocki@samsung.com>
  12
  13 description: |
  14   The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices
  15   represented by separate device tree nodes. Currently this includes: Fully
  16   Integrated Mobile Camera (FIMC, in the S5P SoCs series known as CAMIF), MIPI
  17   CSIS, FIMC-LITE and FIMC-IS (ISP).
  18
  19 properties:
  20   compatible:
  21     const: samsung,fimc
  22
  23   ranges: true
  24
  25   '#address-cells':
  26     const: 1
  27
  28   '#size-cells':
  29     const: 1
  30
  31   '#clock-cells':
  32     const: 1
  33     description: |
  34       The clock specifier cell stores an index of a clock: 0, 1 for
  35       CAM_A_CLKOUT, CAM_B_CLKOUT clocks respectively.
  36
  37   clocks:
  38     minItems: 2
  39     maxItems: 4
  40
  41   clock-names:
  42     minItems: 2
  43     items:
  44       - const: sclk_cam0
  45       - const: sclk_cam1
  46       - const: pxl_async0
  47       - const: pxl_async1
  48
  49   clock-output-names:
  50     maxItems: 2
  51
  52   parallel-ports:
  53     $ref: /schemas/graph.yaml#/properties/ports
  54     description:
  55       Active parallel video input ports.
  56
  57     patternProperties:
  58       "^port@[01]$":
  59         $ref: /schemas/graph.yaml#/$defs/port-base
  60         description:
  61           Camera A and camera B inputs.
  62
  63         properties:
  64           endpoint:
  65             $ref: /schemas/media/video-interfaces.yaml#
  66             unevaluatedProperties: false
  67
  68   pinctrl-names:
  69     minItems: 1
  70     items:
  71       - const: default
  72       - const: idle
  73       - const: active_a
  74       - const: active_b
  75
  76 patternProperties:
  77   "^csis@[0-9a-f]+$":
  78     type: object
  79     $ref: samsung,exynos4210-csis.yaml#
  80     description: MIPI CSI-2 receiver.
  81
  82   "^fimc@[0-9a-f]+$":
  83     type: object
  84     $ref: samsung,exynos4210-fimc.yaml#
  85     description: Fully Integrated Mobile Camera.
  86
  87   "^fimc-is@[0-9a-f]+$":
  88     type: object
  89     $ref: samsung,exynos4212-fimc-is.yaml#
  90     description: Imaging Subsystem (FIMC-IS).
  91
  92   "^fimc-lite@[0-9a-f]+$":
  93     type: object
  94     $ref: samsung,exynos4212-fimc-lite.yaml#
  95     description: Camera host interface (FIMC-LITE).
  96
  97 required:
  98   - compatible
  99   - '#address-cells'
 100   - '#clock-cells'
 101   - clocks
 102   - clock-names
 103   - clock-output-names
 104   - ranges
 105   - '#size-cells'
 106
 107 additionalProperties: false
 108
 109 examples:
 110   - |
 111     #include <dt-bindings/clock/exynos4.h>
 112     #include <dt-bindings/gpio/gpio.h>
 113     #include <dt-bindings/interrupt-controller/arm-gic.h>
 114
 115     camera@11800000 {
 116         compatible = "samsung,fimc";
 117         #clock-cells = <1>;
 118         #address-cells = <1>;
 119         #size-cells = <1>;
 120         ranges = <0x0 0x0 0x18000000>;
 121
 122         clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
 123                  <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
 124         clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 125         clock-output-names = "cam_a_clkout", "cam_b_clkout";
 126
 127         assigned-clocks = <&clock CLK_MOUT_CAM0>,
 128                           <&clock CLK_MOUT_CAM1>;
 129         assigned-clock-parents = <&clock CLK_XUSBXTI>,
 130                                  <&clock CLK_XUSBXTI>;
 131
 132         pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
 133         pinctrl-names = "default";
 134
 135         fimc@11800000 {
 136             compatible = "samsung,exynos4212-fimc";
 137             reg = <0x11800000 0x1000>;
 138             interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 139             clocks = <&clock CLK_FIMC0>,
 140                      <&clock CLK_SCLK_FIMC0>;
 141             clock-names = "fimc", "sclk_fimc";
 142             power-domains = <&pd_cam>;
 143             samsung,sysreg = <&sys_reg>;
 144             iommus = <&sysmmu_fimc0>;
 145
 146             samsung,pix-limits = <4224 8192 1920 4224>;
 147             samsung,mainscaler-ext;
 148             samsung,isp-wb;
 149             samsung,cam-if;
 150         };
 151
 152         /* ... FIMC 1-3 */
 153
 154         csis@11880000 {
 155             compatible = "samsung,exynos4210-csis";
 156             reg = <0x11880000 0x4000>;
 157             interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 158             clocks = <&clock CLK_CSIS0>,
 159                      <&clock CLK_SCLK_CSIS0>;
 160             clock-names = "csis", "sclk_csis";
 161             assigned-clocks = <&clock CLK_MOUT_CSIS0>,
 162                               <&clock CLK_SCLK_CSIS0>;
 163             assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
 164             assigned-clock-rates = <0>, <176000000>;
 165
 166             bus-width = <4>;
 167             power-domains = <&pd_cam>;
 168             phys = <&mipi_phy 0>;
 169             phy-names = "csis";
 170             #address-cells = <1>;
 171             #size-cells = <0>;
 172
 173             vddcore-supply = <&ldo8_reg>;
 174             vddio-supply = <&ldo10_reg>;
 175
 176             /* Camera C (3) MIPI CSI-2 (CSIS0) */
 177             port@3 {
 178                 reg = <3>;
 179                 endpoint {
 180                     remote-endpoint = <&s5c73m3_ep>;
 181                     data-lanes = <1 2 3 4>;
 182                     samsung,csis-hs-settle = <12>;
 183                 };
 184             };
 185         };
 186
 187         /* ... CSIS 1 */
 188
 189         fimc-lite@12390000 {
 190               compatible = "samsung,exynos4212-fimc-lite";
 191               reg = <0x12390000 0x1000>;
 192               interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 193               power-domains = <&pd_isp>;
 194               clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
 195               clock-names = "flite";
 196               iommus = <&sysmmu_fimc_lite0>;
 197         };
 198
 199         /* ... FIMC-LITE 1 */
 200
 201         fimc-is@12000000 {
 202             compatible = "samsung,exynos4212-fimc-is";
 203             reg = <0x12000000 0x260000>;
 204             interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 205                          <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 206             clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
 207                      <&isp_clock CLK_ISP_FIMC_LITE1>,
 208                      <&isp_clock CLK_ISP_PPMUISPX>,
 209                      <&isp_clock CLK_ISP_PPMUISPMX>,
 210                      <&isp_clock CLK_ISP_FIMC_ISP>,
 211                      <&isp_clock CLK_ISP_FIMC_DRC>,
 212                      <&isp_clock CLK_ISP_FIMC_FD>,
 213                      <&isp_clock CLK_ISP_MCUISP>,
 214                      <&isp_clock CLK_ISP_GICISP>,
 215                      <&isp_clock CLK_ISP_MCUCTL_ISP>,
 216                      <&isp_clock CLK_ISP_PWM_ISP>,
 217                      <&isp_clock CLK_ISP_DIV_ISP0>,
 218                      <&isp_clock CLK_ISP_DIV_ISP1>,
 219                      <&isp_clock CLK_ISP_DIV_MCUISP0>,
 220                      <&isp_clock CLK_ISP_DIV_MCUISP1>,
 221                      <&clock CLK_MOUT_MPLL_USER_T>,
 222                      <&clock CLK_ACLK200>,
 223                      <&clock CLK_ACLK400_MCUISP>,
 224                      <&clock CLK_DIV_ACLK200>,
 225                      <&clock CLK_DIV_ACLK400_MCUISP>,
 226                      <&clock CLK_UART_ISP_SCLK>;
 227             clock-names = "lite0", "lite1", "ppmuispx",
 228                           "ppmuispmx", "isp",
 229                           "drc", "fd", "mcuisp",
 230                           "gicisp", "mcuctl_isp", "pwm_isp",
 231                           "ispdiv0", "ispdiv1", "mcuispdiv0",
 232                           "mcuispdiv1", "mpll", "aclk200",
 233                           "aclk400mcuisp", "div_aclk200",
 234                           "div_aclk400mcuisp", "uart";
 235             iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
 236                      <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
 237             iommu-names = "isp", "drc", "fd", "mcuctl";
 238             power-domains = <&pd_isp>;
 239
 240             #address-cells = <1>;
 241             #size-cells = <1>;
 242             ranges;
 243
 244             pmu@10020000 {
 245                 reg = <0x10020000 0x3000>;
 246             };
 247
 248             i2c-isp@12140000 {
 249                 compatible = "samsung,exynos4212-i2c-isp";
 250                 reg = <0x12140000 0x100>;
 251                 clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
 252                 clock-names = "i2c_isp";
 253                 pinctrl-0 = <&fimc_is_i2c1>;
 254                 pinctrl-names = "default";
 255                 #address-cells = <1>;
 256                 #size-cells = <0>;
 257
 258                 image-sensor@10 {
 259                     compatible = "samsung,s5k6a3";
 260                     reg = <0x10>;
 261                     svdda-supply = <&cam_io_reg>;
 262                     svddio-supply = <&ldo19_reg>;
 263                     afvdd-supply = <&ldo19_reg>;
 264                     clock-frequency = <24000000>;
 265                     /* CAM_B_CLKOUT */
 266                     clocks = <&camera 1>;
 267                     clock-names = "extclk";
 268                     gpios = <&gpm1 6 GPIO_ACTIVE_LOW>;
 269
 270                     port {
 271                         endpoint {
 272                             remote-endpoint = <&csis1_ep>;
 273                             data-lanes = <1>;
 274                         };
 275                     };
 276                 };
 277             };
 278         };
 279     };