1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Mediatek Video Decode Accelerator
11 - Yunfei Dong <yunfei.dong@mediatek.com>
14 Mediatek Video Decode is the video decode hardware present in Mediatek
15 SoCs which supports high resolution decoding functionalities.
20 - mediatek,mt8173-vcodec-dec
21 - mediatek,mt8183-vcodec-dec
39 assigned-clock-parents: true
41 assigned-clock-rates: true
50 List of the hardware port in respective IOMMU block for current Socs.
51 Refer to bindings/iommu/mediatek,iommu.yaml.
54 $ref: /schemas/types.yaml#/definitions/phandle
56 Describes point to vpu.
59 $ref: /schemas/types.yaml#/definitions/phandle
61 Describes point to scp.
71 - assigned-clock-parents
79 - mediatek,mt8183-vcodec-dec
99 - mediatek,mt8173-vcodec-dec
114 - const: clk_cci400_sel
119 - const: vdec_bus_clk_src
121 additionalProperties: false
125 #include <dt-bindings/interrupt-controller/arm-gic.h>
126 #include <dt-bindings/clock/mt8173-clk.h>
127 #include <dt-bindings/memory/mt8173-larb-port.h>
128 #include <dt-bindings/interrupt-controller/irq.h>
129 #include <dt-bindings/power/mt8173-power.h>
131 vcodec_dec: vcodec@16000000 {
132 compatible = "mediatek,mt8173-vcodec-dec";
133 reg = <0x16000000 0x100>, /*VDEC_SYS*/
134 <0x16020000 0x1000>, /*VDEC_MISC*/
135 <0x16021000 0x800>, /*VDEC_LD*/
136 <0x16021800 0x800>, /*VDEC_TOP*/
137 <0x16022000 0x1000>, /*VDEC_CM*/
138 <0x16023000 0x1000>, /*VDEC_AD*/
139 <0x16024000 0x1000>, /*VDEC_AV*/
140 <0x16025000 0x1000>, /*VDEC_PP*/
141 <0x16026800 0x800>, /*VP8_VD*/
142 <0x16027000 0x800>, /*VP6_VD*/
143 <0x16027800 0x800>, /*VP8_VL*/
144 <0x16028400 0x400>; /*VP9_VD*/
145 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
146 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
147 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
148 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
149 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
150 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
151 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
152 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
153 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
154 mediatek,vpu = <&vpu>;
155 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
156 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
157 <&topckgen CLK_TOP_UNIVPLL_D2>,
158 <&topckgen CLK_TOP_CCI400_SEL>,
159 <&topckgen CLK_TOP_VDEC_SEL>,
160 <&topckgen CLK_TOP_VCODECPLL>,
161 <&apmixedsys CLK_APMIXED_VENCPLL>,
162 <&topckgen CLK_TOP_VENC_LT_SEL>,
163 <&topckgen CLK_TOP_VCODECPLL_370P5>;
164 clock-names = "vcodecpll",
172 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
173 <&topckgen CLK_TOP_CCI400_SEL>,
174 <&topckgen CLK_TOP_VDEC_SEL>,
175 <&apmixedsys CLK_APMIXED_VCODECPLL>,
176 <&apmixedsys CLK_APMIXED_VENCPLL>;
177 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
178 <&topckgen CLK_TOP_UNIVPLL_D2>,
179 <&topckgen CLK_TOP_VCODECPLL>;
180 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;