media: dt-bindings: mediatek,vcodec: Allow single clock for mt8183
[platform/kernel/linux-starfive.git] / Documentation / devicetree / bindings / media / mediatek,vcodec-decoder.yaml
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
3 %YAML 1.2
4 ---
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7
8 title: Mediatek Video Decode Accelerator
9
10 maintainers:
11   - Yunfei Dong <yunfei.dong@mediatek.com>
12
13 description: |+
14   Mediatek Video Decode is the video decode hardware present in Mediatek
15   SoCs which supports high resolution decoding functionalities.
16
17 properties:
18   compatible:
19     enum:
20       - mediatek,mt8173-vcodec-dec
21       - mediatek,mt8183-vcodec-dec
22
23   reg:
24     maxItems: 12
25
26   interrupts:
27     maxItems: 1
28
29   clocks:
30     minItems: 1
31     maxItems: 8
32
33   clock-names:
34     minItems: 1
35     maxItems: 8
36
37   assigned-clocks: true
38
39   assigned-clock-parents: true
40
41   assigned-clock-rates: true
42
43   power-domains:
44     maxItems: 1
45
46   iommus:
47     minItems: 1
48     maxItems: 32
49     description: |
50       List of the hardware port in respective IOMMU block for current Socs.
51       Refer to bindings/iommu/mediatek,iommu.yaml.
52
53   mediatek,vpu:
54     $ref: /schemas/types.yaml#/definitions/phandle
55     description:
56       Describes point to vpu.
57
58   mediatek,scp:
59     $ref: /schemas/types.yaml#/definitions/phandle
60     description:
61       Describes point to scp.
62
63 required:
64   - compatible
65   - reg
66   - interrupts
67   - clocks
68   - clock-names
69   - iommus
70   - assigned-clocks
71   - assigned-clock-parents
72
73 allOf:
74   - if:
75       properties:
76         compatible:
77           contains:
78             enum:
79               - mediatek,mt8183-vcodec-dec
80
81     then:
82       required:
83         - mediatek,scp
84
85       properties:
86         clocks:
87           minItems: 1
88           maxItems: 1
89
90         clock-names:
91           items:
92             - const: vdec
93
94   - if:
95       properties:
96         compatible:
97           contains:
98             enum:
99               - mediatek,mt8173-vcodec-dec
100
101     then:
102       required:
103         - mediatek,vpu
104
105       properties:
106         clocks:
107           minItems: 8
108           maxItems: 8
109
110         clock-names:
111           items:
112             - const: vcodecpll
113             - const: univpll_d2
114             - const: clk_cci400_sel
115             - const: vdec_sel
116             - const: vdecpll
117             - const: vencpll
118             - const: venc_lt_sel
119             - const: vdec_bus_clk_src
120
121 additionalProperties: false
122
123 examples:
124   - |
125     #include <dt-bindings/interrupt-controller/arm-gic.h>
126     #include <dt-bindings/clock/mt8173-clk.h>
127     #include <dt-bindings/memory/mt8173-larb-port.h>
128     #include <dt-bindings/interrupt-controller/irq.h>
129     #include <dt-bindings/power/mt8173-power.h>
130
131     vcodec_dec: vcodec@16000000 {
132       compatible = "mediatek,mt8173-vcodec-dec";
133       reg = <0x16000000 0x100>,   /*VDEC_SYS*/
134           <0x16020000 0x1000>,  /*VDEC_MISC*/
135           <0x16021000 0x800>,   /*VDEC_LD*/
136           <0x16021800 0x800>,   /*VDEC_TOP*/
137           <0x16022000 0x1000>,  /*VDEC_CM*/
138           <0x16023000 0x1000>,  /*VDEC_AD*/
139           <0x16024000 0x1000>,  /*VDEC_AV*/
140           <0x16025000 0x1000>,  /*VDEC_PP*/
141           <0x16026800 0x800>,   /*VP8_VD*/
142           <0x16027000 0x800>,   /*VP6_VD*/
143           <0x16027800 0x800>,   /*VP8_VL*/
144           <0x16028400 0x400>;   /*VP9_VD*/
145       interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
146       iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
147              <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
148              <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
149              <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
150              <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
151              <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
152              <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
153              <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
154       mediatek,vpu = <&vpu>;
155       power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
156       clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
157              <&topckgen CLK_TOP_UNIVPLL_D2>,
158              <&topckgen CLK_TOP_CCI400_SEL>,
159              <&topckgen CLK_TOP_VDEC_SEL>,
160              <&topckgen CLK_TOP_VCODECPLL>,
161              <&apmixedsys CLK_APMIXED_VENCPLL>,
162              <&topckgen CLK_TOP_VENC_LT_SEL>,
163              <&topckgen CLK_TOP_VCODECPLL_370P5>;
164       clock-names = "vcodecpll",
165                   "univpll_d2",
166                   "clk_cci400_sel",
167                   "vdec_sel",
168                   "vdecpll",
169                   "vencpll",
170                   "venc_lt_sel",
171                   "vdec_bus_clk_src";
172       assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
173                       <&topckgen CLK_TOP_CCI400_SEL>,
174                       <&topckgen CLK_TOP_VDEC_SEL>,
175                       <&apmixedsys CLK_APMIXED_VCODECPLL>,
176                       <&apmixedsys CLK_APMIXED_VENCPLL>;
177       assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
178                              <&topckgen CLK_TOP_UNIVPLL_D2>,
179                              <&topckgen CLK_TOP_VCODECPLL>;
180       assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
181     };