1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies Inc GPI DMA controller
10 - Vinod Koul <vkoul@kernel.org>
13 QCOM GPI DMA controller provides DMA capabilities for
14 peripheral buses such as I2C, UART, and SPI.
17 - $ref: "dma-controller.yaml#"
30 Interrupt lines for each GPI instance
36 DMA clients must use the format described in dma.txt, giving a phandle
37 to the DMA controller plus the following 3 integer cells:
38 - channel: if set to 0xffffffff, any available channel will be allocated
39 for the client. Otherwise, the exact channel specified will be used.
40 - seid: serial id of the client as defined in the SoC documentation.
41 - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h
61 additionalProperties: false
65 #include <dt-bindings/interrupt-controller/arm-gic.h>
66 #include <dt-bindings/dma/qcom-gpi.h>
67 gpi_dma0: dma-controller@800000 {
68 compatible = "qcom,gpi-dma";
70 reg = <0x00800000 0x60000>;
71 iommus = <&apps_smmu 0x0016 0x0>;
73 dma-channel-mask = <0xfa>;
74 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;