Documentation/devicetree/bindings/dma/fsl,edma.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Freescale enhanced Direct Memory Access(eDMA) Controller
   8
   9 description: |
  10   The eDMA channels have multiplex capability by programmable
  11   memory-mapped registers. channels are split into two groups, called
  12   DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed
  13   by any channel of certain group, DMAMUX0 or DMAMUX1, but not both.
  14
  15 maintainers:
  16   - Peng Fan <peng.fan@nxp.com>
  17
  18 properties:
  19   compatible:
  20     oneOf:
  21       - enum:
  22           - fsl,vf610-edma
  23           - fsl,imx7ulp-edma
  24       - items:
  25           - const: fsl,ls1028a-edma
  26           - const: fsl,vf610-edma
  27
  28   reg:
  29     minItems: 2
  30     maxItems: 3
  31
  32   interrupts:
  33     minItems: 2
  34     maxItems: 17
  35
  36   interrupt-names:
  37     minItems: 2
  38     maxItems: 17
  39
  40   "#dma-cells":
  41     const: 2
  42
  43   dma-channels:
  44     const: 32
  45
  46   clocks:
  47     maxItems: 2
  48
  49   clock-names:
  50     maxItems: 2
  51
  52   big-endian:
  53     description: |
  54       If present registers and hardware scatter/gather descriptors of the
  55       eDMA are implemented in big endian mode, otherwise in little mode.
  56     type: boolean
  57
  58 required:
  59   - "#dma-cells"
  60   - compatible
  61   - reg
  62   - interrupts
  63   - clocks
  64   - dma-channels
  65
  66 allOf:
  67   - $ref: "dma-controller.yaml#"
  68   - if:
  69       properties:
  70         compatible:
  71           contains:
  72             const: fsl,vf610-edma
  73     then:
  74       properties:
  75         clock-names:
  76           items:
  77             - const: dmamux0
  78             - const: dmamux1
  79         interrupts:
  80           maxItems: 2
  81         interrupt-names:
  82           items:
  83             - const: edma-tx
  84             - const: edma-err
  85         reg:
  86           maxItems: 3
  87
  88   - if:
  89       properties:
  90         compatible:
  91           contains:
  92             const: fsl,imx7ulp-edma
  93     then:
  94       properties:
  95         clock-names:
  96           items:
  97             - const: dma
  98             - const: dmamux0
  99         interrupts:
 100           maxItems: 17
 101         reg:
 102           maxItems: 2
 103
 104 unevaluatedProperties: false
 105
 106 examples:
 107   - |
 108     #include <dt-bindings/interrupt-controller/arm-gic.h>
 109     #include <dt-bindings/clock/vf610-clock.h>
 110
 111     edma0: dma-controller@40018000 {
 112       #dma-cells = <2>;
 113       compatible = "fsl,vf610-edma";
 114       reg = <0x40018000 0x2000>,
 115             <0x40024000 0x1000>,
 116             <0x40025000 0x1000>;
 117       interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 118                    <0 9 IRQ_TYPE_LEVEL_HIGH>;
 119       interrupt-names = "edma-tx", "edma-err";
 120       dma-channels = <32>;
 121       clock-names = "dmamux0", "dmamux1";
 122       clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>;
 123     };
 124
 125   - |
 126     #include <dt-bindings/interrupt-controller/arm-gic.h>
 127     #include <dt-bindings/clock/imx7ulp-clock.h>
 128
 129     edma1: dma-controller@40080000 {
 130       #dma-cells = <2>;
 131       compatible = "fsl,imx7ulp-edma";
 132       reg = <0x40080000 0x2000>,
 133             <0x40210000 0x1000>;
 134       dma-channels = <32>;
 135       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 136                    <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 137                    <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 138                    <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 139                    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 140                    <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 141                    <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 142                    <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 143                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 144                    <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 145                    <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 146                    <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 147                    <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 148                    <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 149                    <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 150                    <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 151                    /* last is eDMA2-ERR interrupt */
 152                    <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 153        clock-names = "dma", "dmamux0";
 154        clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
 155     };