1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC display controller (VOP2)
10 VOP2 (Video Output Processor v2) is the display controller for the Rockchip
11 series of SoCs which transfers the image data from a video memory
12 buffer to an external LCD interface.
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
27 Must contain one entry corresponding to the base address and length
28 of the register space.
30 Can optionally contain a second entry corresponding to
31 the CRTC gamma LUT address.
41 The VOP interrupt is shared by several interrupt sources, such as
42 frame start (VSYNC), line flag and other status interrupts.
46 - description: Clock for ddr buffer transfer.
47 - description: Clock for the ahb bus to R/W the phy regs.
48 - description: Pixel clock for video port 0.
49 - description: Pixel clock for video port 1.
50 - description: Pixel clock for video port 2.
61 $ref: /schemas/types.yaml#/definitions/phandle
63 Phandle to GRF regs used for misc control
66 $ref: /schemas/graph.yaml#/properties/ports
70 $ref: /schemas/graph.yaml#/properties/port
72 Output endpoint of VP0
75 $ref: /schemas/graph.yaml#/properties/port
77 Output endpoint of VP1
80 $ref: /schemas/graph.yaml#/properties/port
82 Output endpoint of VP2
99 additionalProperties: false
103 #include <dt-bindings/clock/rk3568-cru.h>
104 #include <dt-bindings/interrupt-controller/arm-gic.h>
105 #include <dt-bindings/power/rk3568-power.h>
107 #address-cells = <2>;
110 compatible = "rockchip,rk3568-vop";
111 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
112 reg-names = "vop", "gamma-lut";
113 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&cru ACLK_VOP>,
119 clock-names = "aclk",
124 power-domains = <&power RK3568_PD_VO>;
127 #address-cells = <1>;
131 #address-cells = <1>;
136 #address-cells = <1>;
141 #address-cells = <1>;