Documentation/devicetree/bindings/display/msm/qcom,sm8150-mdss.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SM8150 Display MDSS
   8
   9 maintainers:
  10   - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  11
  12 description:
  13   Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  14   sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  15   bindings of MDSS are mentioned for SM8150 target.
  16
  17 $ref: /schemas/display/msm/mdss-common.yaml#
  18
  19 properties:
  20   compatible:
  21     items:
  22       - const: qcom,sm8150-mdss
  23
  24   clocks:
  25     items:
  26       - description: Display AHB clock from gcc
  27       - description: Display hf axi clock
  28       - description: Display sf axi clock
  29       - description: Display core clock
  30
  31   clock-names:
  32     items:
  33       - const: iface
  34       - const: bus
  35       - const: nrt_bus
  36       - const: core
  37
  38   iommus:
  39     maxItems: 1
  40
  41   interconnects:
  42     maxItems: 2
  43
  44   interconnect-names:
  45     maxItems: 2
  46
  47 patternProperties:
  48   "^display-controller@[0-9a-f]+$":
  49     type: object
  50     properties:
  51       compatible:
  52         const: qcom,sm8150-dpu
  53
  54   "^dsi@[0-9a-f]+$":
  55     type: object
  56     properties:
  57       compatible:
  58         items:
  59           - const: qcom,sm8150-dsi-ctrl
  60           - const: qcom,mdss-dsi-ctrl
  61
  62   "^phy@[0-9a-f]+$":
  63     type: object
  64     properties:
  65       compatible:
  66         const: qcom,dsi-phy-7nm
  67
  68 unevaluatedProperties: false
  69
  70 examples:
  71   - |
  72     #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
  73     #include <dt-bindings/clock/qcom,gcc-sm8150.h>
  74     #include <dt-bindings/clock/qcom,rpmh.h>
  75     #include <dt-bindings/interrupt-controller/arm-gic.h>
  76     #include <dt-bindings/interconnect/qcom,sm8150.h>
  77     #include <dt-bindings/power/qcom-rpmpd.h>
  78
  79     display-subsystem@ae00000 {
  80         compatible = "qcom,sm8150-mdss";
  81         reg = <0x0ae00000 0x1000>;
  82         reg-names = "mdss";
  83
  84         interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
  85                         <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
  86         interconnect-names = "mdp0-mem", "mdp1-mem";
  87
  88         power-domains = <&dispcc MDSS_GDSC>;
  89
  90         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
  91                  <&gcc GCC_DISP_HF_AXI_CLK>,
  92                  <&gcc GCC_DISP_SF_AXI_CLK>,
  93                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
  94         clock-names = "iface", "bus", "nrt_bus", "core";
  95
  96         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  97         interrupt-controller;
  98         #interrupt-cells = <1>;
  99
 100         iommus = <&apps_smmu 0x800 0x420>;
 101
 102         #address-cells = <1>;
 103         #size-cells = <1>;
 104         ranges;
 105
 106         display-controller@ae01000 {
 107             compatible = "qcom,sm8150-dpu";
 108             reg = <0x0ae01000 0x8f000>,
 109                   <0x0aeb0000 0x2008>;
 110             reg-names = "mdp", "vbif";
 111
 112             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 113                      <&gcc GCC_DISP_HF_AXI_CLK>,
 114                      <&dispcc DISP_CC_MDSS_MDP_CLK>,
 115                      <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 116             clock-names = "iface", "bus", "core", "vsync";
 117
 118             assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 119             assigned-clock-rates = <19200000>;
 120
 121             operating-points-v2 = <&mdp_opp_table>;
 122             power-domains = <&rpmhpd SM8150_MMCX>;
 123
 124             interrupt-parent = <&mdss>;
 125             interrupts = <0>;
 126
 127             ports {
 128                 #address-cells = <1>;
 129                 #size-cells = <0>;
 130
 131                 port@0 {
 132                     reg = <0>;
 133                     dpu_intf1_out: endpoint {
 134                         remote-endpoint = <&dsi0_in>;
 135                     };
 136                 };
 137
 138                 port@1 {
 139                     reg = <1>;
 140                     dpu_intf2_out: endpoint {
 141                         remote-endpoint = <&dsi1_in>;
 142                     };
 143                 };
 144             };
 145
 146             mdp_opp_table: opp-table {
 147                 compatible = "operating-points-v2";
 148
 149                 opp-171428571 {
 150                     opp-hz = /bits/ 64 <171428571>;
 151                     required-opps = <&rpmhpd_opp_low_svs>;
 152                 };
 153
 154                 opp-300000000 {
 155                     opp-hz = /bits/ 64 <300000000>;
 156                     required-opps = <&rpmhpd_opp_svs>;
 157                 };
 158
 159                 opp-345000000 {
 160                     opp-hz = /bits/ 64 <345000000>;
 161                     required-opps = <&rpmhpd_opp_svs_l1>;
 162                 };
 163
 164                 opp-460000000 {
 165                     opp-hz = /bits/ 64 <460000000>;
 166                     required-opps = <&rpmhpd_opp_nom>;
 167                 };
 168             };
 169         };
 170
 171         dsi@ae94000 {
 172             compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 173             reg = <0x0ae94000 0x400>;
 174             reg-names = "dsi_ctrl";
 175
 176             interrupt-parent = <&mdss>;
 177             interrupts = <4>;
 178
 179             clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
 180                      <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 181                      <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 182                      <&dispcc DISP_CC_MDSS_ESC0_CLK>,
 183                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 184                      <&gcc GCC_DISP_HF_AXI_CLK>;
 185             clock-names = "byte",
 186                           "byte_intf",
 187                           "pixel",
 188                           "core",
 189                           "iface",
 190                           "bus";
 191
 192             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
 193                               <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
 194             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
 195
 196             operating-points-v2 = <&dsi_opp_table>;
 197             power-domains = <&rpmhpd SM8150_MMCX>;
 198
 199             phys = <&dsi0_phy>;
 200             phy-names = "dsi";
 201
 202             #address-cells = <1>;
 203             #size-cells = <0>;
 204
 205             ports {
 206                 #address-cells = <1>;
 207                 #size-cells = <0>;
 208
 209                 port@0 {
 210                     reg = <0>;
 211                     dsi0_in: endpoint {
 212                         remote-endpoint = <&dpu_intf1_out>;
 213                     };
 214                 };
 215
 216                 port@1 {
 217                     reg = <1>;
 218                     dsi0_out: endpoint {
 219                     };
 220                 };
 221             };
 222
 223             dsi_opp_table: opp-table {
 224                 compatible = "operating-points-v2";
 225
 226                 opp-187500000 {
 227                     opp-hz = /bits/ 64 <187500000>;
 228                     required-opps = <&rpmhpd_opp_low_svs>;
 229                 };
 230
 231                 opp-300000000 {
 232                     opp-hz = /bits/ 64 <300000000>;
 233                     required-opps = <&rpmhpd_opp_svs>;
 234                 };
 235
 236                 opp-358000000 {
 237                     opp-hz = /bits/ 64 <358000000>;
 238                     required-opps = <&rpmhpd_opp_svs_l1>;
 239                 };
 240             };
 241         };
 242
 243         dsi0_phy: phy@ae94400 {
 244             compatible = "qcom,dsi-phy-7nm";
 245             reg = <0x0ae94400 0x200>,
 246                   <0x0ae94600 0x280>,
 247                   <0x0ae94900 0x260>;
 248             reg-names = "dsi_phy",
 249                         "dsi_phy_lane",
 250                         "dsi_pll";
 251
 252             #clock-cells = <1>;
 253             #phy-cells = <0>;
 254
 255             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 256                      <&rpmhcc RPMH_CXO_CLK>;
 257             clock-names = "iface", "ref";
 258             vdds-supply = <&vreg_dsi_phy>;
 259         };
 260
 261         dsi@ae96000 {
 262             compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 263             reg = <0x0ae96000 0x400>;
 264             reg-names = "dsi_ctrl";
 265
 266             interrupt-parent = <&mdss>;
 267             interrupts = <5>;
 268
 269             clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
 270                      <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
 271                      <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
 272                      <&dispcc DISP_CC_MDSS_ESC1_CLK>,
 273                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 274                      <&gcc GCC_DISP_HF_AXI_CLK>;
 275             clock-names = "byte",
 276                           "byte_intf",
 277                           "pixel",
 278                           "core",
 279                           "iface",
 280                           "bus";
 281
 282             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
 283                               <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
 284             assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
 285
 286             operating-points-v2 = <&dsi_opp_table>;
 287             power-domains = <&rpmhpd SM8150_MMCX>;
 288
 289             phys = <&dsi1_phy>;
 290             phy-names = "dsi";
 291
 292             #address-cells = <1>;
 293             #size-cells = <0>;
 294
 295             ports {
 296                 #address-cells = <1>;
 297                 #size-cells = <0>;
 298
 299                 port@0 {
 300                     reg = <0>;
 301                     dsi1_in: endpoint {
 302                         remote-endpoint = <&dpu_intf2_out>;
 303                     };
 304                 };
 305
 306                 port@1 {
 307                     reg = <1>;
 308                     dsi1_out: endpoint {
 309                     };
 310                 };
 311             };
 312         };
 313
 314         dsi1_phy: phy@ae96400 {
 315             compatible = "qcom,dsi-phy-7nm";
 316             reg = <0x0ae96400 0x200>,
 317                   <0x0ae96600 0x280>,
 318                   <0x0ae96900 0x260>;
 319             reg-names = "dsi_phy",
 320                         "dsi_phy_lane",
 321                         "dsi_pll";
 322
 323             #clock-cells = <1>;
 324             #phy-cells = <0>;
 325
 326             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 327                      <&rpmhcc RPMH_CXO_CLK>;
 328             clock-names = "iface", "ref";
 329             vdds-supply = <&vreg_dsi_phy>;
 330         };
 331     };
 332 ...